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    SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME
    3.
    发明公开
    SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME 审中-公开

    公开(公告)号：US20240324232A1

    公开(公告)日：2024-09-26

    申请号：US18400953

    申请日：2023-12-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Minsu Jeong ,  Ahreum Kim ,  Pansuk Kwak

    IPC: H10B43/40 ,  H01L23/522 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

    CPC classification number: H10B43/40 ,  H01L23/5223 ,  H01L28/86 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

    Abstract: An example semiconductor device includes a first electrode structure, including a first connection portion and first finger portions extending from the first connection portion, and a second electrode structure, including a second connection portion and second finger portions extending from the second connection portion and alternately arranged with the first finger portions. The first electrode structure may include first lines and first contacts alternately stacked, the second electrode structure may include second lines and second contacts alternately stacked, and the first and second lines and the first and second contacts may be arranged at a first pitch on N levels among a plurality of levels, and are arranged at a second pitch greater than the first pitch on M levels of the plurality of levels, where N may be 3 or more, and M may be less than N.

    Clock gating cell with low power and integrated circuit including the same
    6.
    发明授权
    Clock gating cell with low power and integrated circuit including the same 有权

    公开(公告)号：US11190186B2

    公开(公告)日：2021-11-30

    申请号：US17222197

    申请日：2021-04-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Youngo Lee ,  Ahreum Kim

    IPC: H03K19/00 ,  H03K3/012

    Abstract: In an integrated circuit including a clock gating cell based on a set-reset (SR) latch, the clock gating cell includes a first 2-input logic gate configured to receive a clock input and a first signal, and generate a second signal, a first inverter configured to receive the second signal, and generate a clock output, and a 4-input logic gate including a 4-input keeping logic gate configured to generate the SR latch by being cross-coupled to the first 2-input logic gate and keep a level of the first signal.

    Integrated clock gating circuit
    7.
    发明授权
    Integrated clock gating circuit 有权

    公开(公告)号：US11063592B2

    公开(公告)日：2021-07-13

    申请号：US16991659

    申请日：2020-08-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Youngo Lee ,  Ahreum Kim ,  Minsu Kim

    IPC: H03K19/00 ,  H03K3/037 ,  H03K3/33 ,  G06F1/08 ,  H03K17/687

    Abstract: An integrated circuit gating circuit includes a first control stage that outputs a first internal signal based on an enable signal and a clock signal, a second control stage that outputs a second internal signal based on the first internal signal and the clock signal, and an output driver that outputs an output clock signal based on the second internal signal. The second control stage includes a first multi-finger transistor that is connected between a second node outputting the second internal signal and the 0-th node and operates based on the clock signal. A first portion of the first multi-finger transistor is formed in a first row defined on a semiconductor substrate, and a second portion of the first multi-finger transistor is formed in a second row defined on the semiconductor substrate.

    Integrated clock gating cell and integrated circuit including the same
    8.
    发明授权
    Integrated clock gating cell and integrated circuit including the same 有权

    公开(公告)号：US10944401B1

    公开(公告)日：2021-03-09

    申请号：US16913484

    申请日：2020-06-26

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ahreum Kim

    IPC: H03K19/096 ,  H03K19/00 ,  H03K3/037

    Abstract: A clock gating cell includes an input logic/latch circuit, a keeper logic/signal generating circuit, and an output driver. The input logic/latch circuit generates an internal enable signal based on first and second input enable signals, and generates a first internal signal provided to a first node based on the internal enable signal and an input clock signal. The keeper logic/signal generating circuit is connected between the first node and a second node, includes a feedback path feeding back the first internal signal, generates a second internal signal provided to the second node based on the first internal signal and the input clock signal, and includes first and second paths discharging the second node. The first and second paths are different. The second path is connected to the feedback path. The output driver generates an output clock signal based on the second internal signal.

    Active resistor array of semiconductor memory device
    10.
    发明授权
    Active resistor array of semiconductor memory device 有权

    公开(公告)号：US12082406B2

    公开(公告)日：2024-09-03

    申请号：US17883842

    申请日：2022-08-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ansoo Park ,  Ahreum Kim

    IPC: G11C11/418 ,  H01L27/08 ,  H10B41/10 ,  H10B41/35 ,  H10B41/41

    CPC classification number: H10B41/35 ,  H01L27/0802 ,  H10B41/10 ,  H10B41/41

    Abstract: An active resistor array of a semiconductor memory device comprises a first active resistor in a first active resistor region; a second active resistor in the first active resistor region and arranged in parallel with the first active resistor, and an isolation element layer interposed therebetween; a third active resistor formed in a second active resistor region; a first selection transistor formed in a first selection transistor region and connected to the second active resistor; and a second selection transistor formed in a second selection transistor region and connected to the third active resistor. The first and second selection transistors are connected to the same gate layer. The gate layer of the first and second selection transistors is on the isolation element layer. Since example embodiments may help to ensure the uniformity of the layout pattern, active resistance distribution may be improved due to reduction in process variation.

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