公开(公告)号：US08980689B2

公开(公告)日：2015-03-17

申请号：US14088576

申请日：2013-11-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoung-Soo Kwak ,  Cha-Jea Jo ,  Tae-Je Cho ,  Sang-Uk Han

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L25/00

CPC classification number: H01L25/50 ,  H01L25/0657 ,  H01L2224/13 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a method of fabricating a multi-chip stack package. The method includes preparing single-bodied lower chips having a single-bodied lower chip substrate having a first surface and a second surface disposed opposite the first surface, bonding unit package substrates onto the first surface of the single-bodied lower chip substrate to form a single-bodied substrate-chip bonding structure, separating the single-bodied substrate-chip bonding structure into a plurality of unit substrate-chip bonding structures, preparing single-bodied upper chips having a single-bodied upper chip substrate, bonding the plurality of unit substrate-chip bonding structures onto a first surface of the single-bodied upper chip substrate to form a single-bodied semiconductor chip stack structure, and separating the single-bodied semiconductor chip stack structure into a plurality of unit semiconductor chip stack structures.

Abstract translation: 提供一种制造多芯片堆叠封装的方法。 该方法包括制备具有单体下部芯片衬底的单体下部芯片，其具有第一表面和与第一表面相对设置的第二表面，将单元封装衬底粘合到单体下部芯片衬底的第一表面上以形成 单体衬底芯片接合结构，将单体衬底 - 芯片接合结构分离成多个单元衬底 - 芯片接合结构，制备具有单体上片状衬底的单体上片，将多个单元 衬底 - 芯片接合结构到单体上芯片衬底的第一表面上以形成单体半导体芯片堆叠结构，并将单体半导体芯片堆叠结构分离成多个单元半导体芯片堆栈结构。

公开(公告)号：US09171825B2

公开(公告)日：2015-10-27

申请号：US14488707

申请日：2014-09-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Sick Park ,  In-Young Lee ,  Byoung-Soo Kwak ,  Min-Soo Kim ,  Sang-Wook Park ,  Tae-Je Cho

IPC: H01L23/48 ,  H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L23/36 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/36 ,  H01L23/481 ,  H01L23/49816 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83191 ,  H01L2224/94 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2224/11 ,  H01L2224/27 ,  H01L2924/00

Abstract: A semiconductor device and a method of fabricating the same includes providing a first semiconductor chip which has first connection terminals, providing a second semiconductor chip which comprises top and bottom surfaces facing each other and has second connection terminals and a film-type first underfill material formed on the bottom surface thereof, bonding the first semiconductor chip to a mounting substrate by using the first connection terminals, bonding the first semiconductor chip and the second semiconductor chip by using the first underfill material, and forming a second underfill material which fills a space between the mounting substrate and the first semiconductor chip and covers side surfaces of the first semiconductor chip and at least part of side surfaces of the second semiconductor chip.

Abstract translation: 一种半导体器件及其制造方法包括提供具有第一连接端子的第一半导体芯片，提供第二半导体芯片，该第二半导体芯片包括彼此相对的顶表面和底表面，并且具有第二连接端子和形成的膜型第一底部填充材料 在其底面上，通过使用第一连接端子将第一半导体芯片接合到安装基板，通过使用第一底部填充材料接合第一半导体芯片和第二半导体芯片，以及形成填充第二底部填充材料之间的空间的第二底部填充材料 安装基板和第一半导体芯片，并且覆盖第一半导体芯片的侧表面和第二半导体芯片的至少一部分侧表面。

公开(公告)号：US11824006B2

公开(公告)日：2023-11-21

申请号：US17492788

申请日：2021-10-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byoung-Soo Kwak ,  Ji-Seok Hong

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L23/5384 ,  H01L23/31 ,  H01L23/5386 ,  H01L25/0655

Abstract: A semiconductor package includes a first semiconductor chip having a first face and a second face opposite thereto. The first semiconductor chip includes a first wiring layer having a surface that forms the first face. A second semiconductor chip disposed on the first face of the first semiconductor chip includes a second wiring layer directly contacting the first wiring layer. A first mold layer is disposed on one lateral side of the first semiconductor chip and directly contacts the second wiring layer. A first via penetrates the first mold layer. A width of the first wiring layer and the first semiconductor chip in a horizontal direction are substantially the same. A width of the second wiring layer and the second semiconductor chip in the horizontal direction are substantially the same. A height of the first via and the first semiconductor chip in the vertical direction are substantially the same.

公开(公告)号：US09275903B2

公开(公告)日：2016-03-01

申请号：US14488883

申请日：2014-09-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoung-Soo Kwak ,  Youngsu Kim ,  Sangwook Park ,  Taeje Cho

IPC: H01L21/78 ,  H01L21/02 ,  H01L21/268 ,  H01L21/683 ,  H01L23/544

CPC classification number: H01L21/78 ,  H01L21/02013 ,  H01L21/268 ,  H01L21/6835 ,  H01L23/544 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2223/54493 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor device include preparing an initial substrate including an edge region and a central region in which circuit patterns are formed, forming a reforming region in the edge region of the initial substrate, grinding the initial substrate to form a substrate, and cutting the substrate to form a semiconductor chip including each of the circuit patterns. A crystal structure of the reforming region is different from that of the initial substrate.

Abstract translation: 制造半导体器件的方法包括制备包括边缘区域和形成电路图案的中心区域的初始衬底，在初始衬底的边缘区域中形成重整区域，研磨初始衬底以形成衬底，以及 切割基板以形成包括每个电路图案的半导体芯片。 重整区域的晶体结构与初始衬底的晶体结构不同。