公开(公告)号：US20220238146A1

公开(公告)日：2022-07-28

申请号：US17483010

申请日：2021-09-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byungsuk Woo ,  Changkyu Seol ,  Cheolmin Park ,  Sucheol Lee ,  Chanik Park

IPC: G11C7/22 ,  G11C7/16 ,  H01L25/065

Abstract: A high bandwidth memory system includes a motherboard; and a semiconductor package coupled to the motherboard. The semiconductor package includes a package substrate mounted on the motherboard and including signal lines providing a plurality of channels; a first semiconductor device mounted on the package substrate and including a first physical layer (PHY) circuit; and a second semiconductor device mounted on the package substrate and including a second PHY circuit. The first semiconductor device and the second semiconductor device exchange a data signal with each other through the plurality of channels, the data signal is a multilevel signal having M levels, where M is a natural number greater than 2, and the first PHY circuit compensates for distortion of the channels and performs digital signal processing to compensate for a mismatch between the channels.

公开(公告)号：US12248689B2

公开(公告)日：2025-03-11

申请号：US17847125

申请日：2022-06-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yang Seok Ki ,  Chanik Park ,  Sungwook Ryu

IPC: G06F3/06 ,  H04N19/15 ,  H04N19/423 ,  H04N21/218 ,  H04N21/231 ,  H04N21/232

Abstract: A storage system is disclosed. The storage system may include a first storage device and a second storage device. A receiver may receive an encoded stream. A splitter may identify a first chunk of data in the encoded stream and a second chunk of data in the encoded stream. A distributor may store the first chunk of data on the first storage device and the second chunk of data on the second storage device.

公开(公告)号：US11210208B2

公开(公告)日：2021-12-28

申请号：US16162821

申请日：2018-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae-Jeong Kim ,  Jiseok Kang ,  Tae-Kyeong Ko ,  Sung-Joon Kim ,  Wooseop Kim ,  Chanik Park ,  Wonjae Shin ,  Yongjun Yu ,  Insu Choi

IPC: G06F12/02 ,  G11C11/56 ,  G06F3/06 ,  G06F13/16

Abstract: A memory system includes a nonvolatile memory module and a first controller configured to control the nonvolatile memory module. The nonvolatile memory module includes a volatile memory device, a nonvolatile memory device, and a second controller configured to control the volatile memory device and the nonvolatile memory device. The first controller may be configured to transmit a read request to the second controller. When, during a read operation according to the read request, normal data is not received from the nonvolatile memory device, the first controller may perform one or more retransmits of the read request to the second controller without a limitation on a number of times that the first controller performs the one or more retransmits of the read request.

公开(公告)号：US11194655B2

公开(公告)日：2021-12-07

申请号：US16775587

申请日：2020-01-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jihwan Kim ,  Inyoung Kim ,  Jonghwa Kim ,  Chanik Park

IPC: G06F11/10 ,  G06F11/07 ,  G06F11/30 ,  G06F3/06

Abstract: A storage device includes a non-volatile memory including a plurality of memory blocks and a storage controller configured to control a read operation of the non-volatile memory. The storage controller receives power-off time information indicating a power-off time point at which the storage device is powered off, and power-on time information indicating a power-on time point at which the storage device is powered on, when the storage device is switched from a power-off state to a power-on state. The storage controller stores a power-off time stamp corresponding to the power-off time point and a power-on time stamp corresponding to the power-on time point in the non-volatile memory.

公开(公告)号：US12086242B2

公开(公告)日：2024-09-10

申请号：US17132766

申请日：2020-12-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seongnam Kwon ,  Jisoo Kim ,  Taeseok Hwang ,  Chanik Park

IPC: G06F21/00 ,  G06F3/06 ,  G06F21/33 ,  G06F21/44 ,  G06F21/55 ,  G06F21/56

CPC classification number: G06F21/554 ,  G06F3/0622 ,  G06F3/0634 ,  G06F3/0673 ,  G06F21/33 ,  G06F21/44 ,  G06F21/567 ,  G06F21/568 ,  G06F3/0659 ,  G06F2221/031

Abstract: Disclosed is an operating method of a storage device, which includes detecting virus/malware, performing an authentication operation with a host device when the virus/malware is detected, and entering a recovery mode when the authentication operation indicates that authentication is successful.

公开(公告)号：US11157342B2

公开(公告)日：2021-10-26

申请号：US16164103

申请日：2018-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonjae Shin ,  Tae-Kyeong Ko ,  Dae-Jeong Kim ,  Sung-Joon Kim ,  Wooseop Kim ,  Chanik Park ,  Yongjun Yu ,  Insu Choi ,  Hui-Chung Byun ,  JongYoung Lee

IPC: G06F11/07

Abstract: A memory system includes a processor that includes cores and a memory controller, and a first semiconductor memory module that communicates with the memory controller. The cores receive a call to perform a first exception handling in response to detection of a first error when the memory controller reads first data from the first semiconductor memory module. A first monarchy core of the cores performs the first exception handling and the remaining cores of the cores return to remaining operations previously performed.

公开(公告)号：US09858000B2

公开(公告)日：2018-01-02

申请号：US14978606

申请日：2015-12-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Su-Gon Kim ,  Sangyong Lee ,  Dongbin Park ,  Chanik Park

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0619 ,  G06F3/0652 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246

Abstract: A sustained status accelerating method for a storage device includes: controlling the storage device to receive a sustained status command from the outside; and controlling the storage device to enter the sustained status using a sustained valid page count (SVPC) table in response to the sustained status command so that each of a plurality of blocks constituting the storage device has a value greater than a predetermined valid page count. The SVPC table includes a valid page count with respect to each of the blocks in the storage device.

公开(公告)号：US11631444B2

公开(公告)日：2023-04-18

申请号：US17483010

申请日：2021-09-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byungsuk Woo ,  Changkyu Seol ,  Cheolmin Park ,  Sucheol Lee ,  Chanik Park

IPC: G11C7/22 ,  H01L25/065 ,  G11C7/16 ,  H01L27/108

Abstract: A high bandwidth memory system includes a motherboard; and a semiconductor package coupled to the motherboard. The semiconductor package includes a package substrate mounted on the motherboard and including signal lines providing a plurality of channels; a first semiconductor device mounted on the package substrate and including a first physical layer (PHY) circuit; and a second semiconductor device mounted on the package substrate and including a second PHY circuit. The first semiconductor device and the second semiconductor device exchange a data signal with each other through the plurality of channels, the data signal is a multilevel signal having M levels, where M is a natural number greater than 2, and the first PHY circuit compensates for distortion of the channels and performs digital signal processing to compensate for a mismatch between the channels.

公开(公告)号：US11610624B2

公开(公告)日：2023-03-21

申请号：US17474666

申请日：2021-09-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minsu Kim ,  Namhyung Kim ,  Daejeong Kim ,  Dohan Kim ,  Chanik Park ,  Deokho Seo ,  Wonjae Shin ,  Changmin Lee ,  Ilguy Jung ,  Insu Choi

IPC: G11C11/406

Abstract: Provided are a memory device skipping a refresh operation and an operating method thereof. The memory device includes a memory cell array including N rows; a refresh controller configured to control a refresh operation for the N rows of the memory cell array based on a refresh command; and an access information storage circuit including a plurality of registers configured to store flag information corresponding to each of the N rows, wherein a first value indicates rows that have been accessed, and a second value indicates rows that have not been accessed. The refresh controller is further configured to control whether the refresh operation is performed for a first row of the N rows at a refresh timing for the first row based on the flag information corresponding to the first row.

公开(公告)号：US20220215871A1

公开(公告)日：2022-07-07

申请号：US17406511

申请日：2021-08-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minsu Kim ,  Namhyung Kim ,  Daejeong Kim ,  Dohan Kim ,  Chanik Park ,  Deokho Seo ,  Wonjae Shin ,  Changmin Lee ,  Ilguy Jung ,  Insu Choi

IPC: G11C11/406 ,  G11C11/4076 ,  G11C11/4096

Abstract: Provided are an accelerator controlling a memory device, a computing system including the accelerator, and an operating method of the accelerator. The accelerator includes: a signal control/monitoring circuit configured to detect an entry to a self-refresh mode of a memory device and an exit from the self-refresh mode based on monitoring a signal provided from a host; an accelerator logic configured to generate a first command/address signal and a first piece of data; and a selector configured to output the first command/address signal and the first piece of data to the memory device based on detection of the entry to the self-refresh mode, and output a second command/address signal and a second piece of data provided from the host, to the memory device, based on detection of the exit from the self-refresh mode.