公开(公告)号：US20150380508A1

公开(公告)日：2015-12-31

申请号：US14697782

申请日：2015-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae-ik KIM ,  Hyoung-sub KIM ,  Sung-eui KIM

IPC: H01L29/45 ,  H01L23/528

CPC classification number: H01L27/10855 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10823 ,  H01L27/10885 ,  H01L27/10888

Abstract: A semiconductor device includes a semiconductor substrate including a plurality of active areas, a bit line crossing the plurality of active areas, a direct contact connecting a first active area of the plurality of active areas with the bit line, an insulating spacer covering a side wall of the bit line and extending at a level lower than a level of an upper surface of the semiconductor substrate, a contact pad connected with a side wall of a second active area of the plurality of active areas, which neighbors the first active area, a first insulating pattern defining a contact hole exposing the insulating spacer and the contact pad, and a buried contact connected with the contact pad and filling the contact hole.

Abstract translation: 半导体器件包括：半导体衬底，包括多个有效区域，与多个有源区域交叉的位线;将多个有源区域的第一有源区域与位线连接的直接接触;覆盖侧壁 并且在比半导体衬底的上表面的电平低的水平处延伸的触点焊盘与多个有源区域的与第一有源区域相邻的第二有源区域的侧壁连接的接触焊盘， 第一绝缘图案限定了暴露绝缘间隔件和接触焊盘的接触孔，以及与接触垫连接并填充接触孔的埋入触头。

公开(公告)号：US20150132943A1

公开(公告)日：2015-05-14

申请号：US14539558

申请日：2014-11-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae-ik KIM ,  Hyoung-sub KIM ,  Yoo-sang HWANG

IPC: H01L21/768 ,  H01L27/105 ,  H01L21/311

CPC classification number: H01L27/10823 ,  H01L27/10814 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10891

Abstract: Provided is a method of manufacturing a semiconductor device. The method includes forming isolated contact filling portions and an etch control portion, the isolated contact filling portions filling contact holes defined in a support layer and are spaced apart from each other in a first direction and a second direction perpendicular to the first direction and the etch control layer surrounding the isolated contact filling portions, forming an interconnection layer on the isolated contact filling portions and the etch control portion, and forming interconnection patterns by photo-etching the interconnection layer, the isolated contact patterns, and the etch control portion, the interconnection patterns being relatively narrow in the first direction and relatively wide in the second direction.

Abstract translation: 提供一种制造半导体器件的方法。 该方法包括形成隔离的接触填充部分和蚀刻控制部分，隔离的接触填充部分填充限定在支撑层中的接触孔，并且在垂直于第一方向的第一方向和第二方向彼此间隔开，并且蚀刻 围绕隔离的接触填充部分的控制层，在隔离的接触填充部分和蚀刻控制部分上形成互连层，以及通过光刻蚀互连层，隔离接触图案和蚀刻控制部分形成互连图案， 图案在第一方向上相对较窄并且在第二方向上相对较宽。

公开(公告)号：US20170062328A1

公开(公告)日：2017-03-02

申请号：US15347103

申请日：2016-11-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Je-min PARK ,  Dae-ik KIM

IPC: H01L23/528 ,  H01L21/3213 ,  G11C8/10 ,  H01L23/535 ,  H01L27/108 ,  G11C7/06 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/528 ,  G11C7/062 ,  G11C8/10 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5221 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/535 ,  H01L23/642 ,  H01L23/647 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/10897 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes: a first interconnection line and a second interconnection line which extend apart from each other on a first plane at a first level on a substrate; a bypass interconnection line that extends on a second plane at a second level on the substrate; and a plurality of contact plugs for connecting the bypass interconnection line to the first interconnection line and the second interconnection line. A method includes forming a bypass interconnection line spaced apart from a substrate and forming on a same plane a plurality of interconnection lines connected to the bypass interconnection line via a plurality of contact plugs.

Abstract translation: 半导体器件包括：第一互连线和第二互连线，其在衬底上的第一层的第一平面上彼此分开; 旁路互连线，其在所述衬底上的第二电平的第二平面上延伸; 以及用于将旁路互连线连接到第一互连线和第二互连线的多个接触插塞。 一种方法包括形成与衬底间隔开的旁路互连线，并且在同一平面上形成多个通过多个接触插塞连接到旁路互连线的互连线。

公开(公告)号：US20150214146A1

公开(公告)日：2015-07-30

申请号：US14591732

申请日：2015-01-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae-ik KIM ,  Hyoung-sub KIM ,  Sung-eui KIM ,  Hoon JEONG

IPC: H01L23/528

CPC classification number: H01L27/10885 ,  H01L27/10855 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate including an active region, a plurality of conductive line structures separate from the substrate, a plurality of contact plugs between the plurality of conductive line structures, a plurality of landing pads connected to a corresponding contact plug of the plurality of contact plugs, a landing pad insulation pattern between the plurality of landing pads, and a first insulation spacer between the landing pad insulation pattern and first conductive line structures from among the plurality of conductive line structures.

Abstract translation: 一种半导体器件包括：衬底，包括有源区，与衬底分离的多个导线结构;多个导线结构之间的多个接触插塞;多个接地焊盘，其连接到多个 接触插塞，多个着陆焊盘之间的着陆焊盘绝缘图案，以及在多个导线结构之间的着陆焊盘绝缘图案和第一导线结构之间的第一绝缘隔离件。

公开(公告)号：US20140252440A1

公开(公告)日：2014-09-11

申请号：US14175305

申请日：2014-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Je-min PARK ,  Dae-ik KIM ,  Ji-young KIM ,  Nak-jin SON ,  Yoo-sang HWANG

IPC: H01L23/48 ,  H01L27/105

CPC classification number: H01L23/485 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10888 ,  H01L29/41791 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices include a substrate having a target connection region; a conductive line having a first side wall spaced apart from the substrate by at least an insulating layer, and a conductive plug structure electrically connecting the conductive line to the target connection region, wherein the conductive plug includes a first conductive plug having a first side wall, a bottom surface contacting the target connection region of the substrate, and a second side wall facing the first side wall of the conductive line, and a second conductive plug between the conductive line and the first conductive plug. The second conductive plug contacts both the first side wall of the conductive line and the second side wall of the first conductive plug.

Abstract translation: 半导体器件包括具有目标连接区域的衬底; 导电线，其具有通过至少绝缘层与衬底间隔开的第一侧壁和将导电线电连接到目标连接区域的导电插塞结构，其中导电插塞包括第一导电插塞，第一导电插塞具有第一侧壁 ，与基板的目标连接区域接触的底表面和面对导电线的第一侧壁的第二侧壁，以及在导线和第一导电塞之间的第二导电塞。 第二导电插头接触导电线的第一侧壁和第一导电插塞的第二侧壁。

公开(公告)号：US20130113029A1

公开(公告)日：2013-05-09

申请号：US13724799

申请日：2012-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyung-woo Chung ,  Yong-chul OH ,  Yoo-sang HWANG ,  Gyo-young JIN ,  Hyeong-sun HONG ,  Dae-ik KIM

IPC: H01L27/108

CPC classification number: H01L27/10805 ,  H01L27/0207 ,  H01L27/10876 ,  H01L27/10885

Abstract: A semiconductor memory device includes a first pair of pillars extending from a substrate to form vertical channel regions, the first pair of pillars having a first pillar and a second pillar adjacent to each other, the first pillar and the second pillar arranged in a first direction, a first bit line disposed on a bottom surface of a first trench formed betweenthe first pair of pillars, the first bit line extending in a second direction that is substantially perpendicular to the first direction, a first contact gate disposed on a first surface of the first pillar with a first gate insulating layer therebetween, a second contact gate disposed on a first surface of the second pillar with a second gate insulating layer therebetween, the first surface of the first pillar and the first surface of the second pillar face opposite directions, and a first word line disposed on the first contact gate and a second word line disposed on the second contact gate, the word lines extending in the first direction.

Abstract translation: 半导体存储器件包括从衬底延伸以形成垂直沟道区的第一对柱，所述第一对柱具有彼此相邻的第一柱和第二柱，所述第一柱和第二柱以第一方向 ，设置在形成在所述第一对柱之间的第一沟槽的底表面上的第一位线，所述第一位线在基本上垂直于所述第一方向的第二方向上延伸;第一接触栅极，设置在第一表面上， 所述第一支柱具有第一栅极绝缘层，第二触点栅极，设置在所述第二支柱的第一表面上，第二栅极绝缘层之间具有第二栅极绝缘层，所述第一支柱的第一表面和所述第二支柱的第一表面面向相反方向 以及设置在第一接触栅极上的第一字线和设置在第二接触栅极上的第二字线，在fi 第一个方向。