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公开(公告)号:US10056454B2
公开(公告)日:2018-08-21
申请号:US15336111
申请日:2016-10-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Ho-Jun Kim , Jong-Ho Lee , Geum-Jong Bae , Dong-Chan Suh
IPC: H01L27/088 , H01L29/06 , H01L29/78 , H01L29/16 , H01L21/8234 , B82Y10/00 , H01L29/423 , H01L29/66 , H01L29/775
CPC classification number: H01L29/0673 , B82Y10/00 , H01L21/823431 , H01L27/0886 , H01L29/0665 , H01L29/16 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/785 , H01L29/78696
Abstract: A semiconductor device includes a semiconductor substrate. A first fin extends in a first direction. A first nano sheet structure includes at least two first nano sheets which extend in the first direction parallel to an upper surface of the first fin. A second fin extends in the first direction. A second nano sheet structure includes at least two second nano sheets which extend in the first direction parallel to an upper surface of the second fin. At least one of the at least two first nano sheets has a different thickness from at least one of the at least two second nano sheets.
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公开(公告)号:US20140024192A1
公开(公告)日:2014-01-23
申请号:US13932047
申请日:2013-07-01
Applicant: Samsung Electronics Co., Ltd.
Inventor: Seok-Hoon Kim , Dong-Chan Suh , Byeong-Chan Lee
IPC: H01L29/66
CPC classification number: H01L29/6656 , H01L21/764 , H01L21/7682 , H01L29/165 , H01L29/4966 , H01L29/517 , H01L29/6653 , H01L29/66545 , H01L29/66636 , H01L29/7848
Abstract: A method for fabricating a semiconductor device comprises forming a dummy gate pattern and a spacer that is arranged on a sidewall of the dummy gate pattern on a substrate, forming an air gap on both sides of the dummy gate pattern by removing the spacer, exposing the substrate by removing the dummy gate pattern, and sequentially forming a gate insulating film including a high-k insulating film and a metal gate electrode on the exposed substrate.
Abstract translation: 一种半导体器件的制造方法,其特征在于,在基板上形成伪栅极图案和间隔物,该间隔物配置在伪栅极图案的侧壁上,通过去除间隔物,在伪栅极图案的两面形成气隙, 通过去除伪栅极图案,并且在暴露的基板上顺序地形成包括高k绝缘膜和金属栅电极的栅极绝缘膜。
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公开(公告)号:US20170256611A1
公开(公告)日:2017-09-07
申请号:US15336111
申请日:2016-10-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: HO-JUN KIM , Jong-ho Lee , Geum-Jong Bae , Dong-Chan Suh
IPC: H01L29/06 , H01L21/8234 , H01L29/16 , H01L29/78 , H01L27/088
CPC classification number: H01L29/0673 , B82Y10/00 , H01L21/823431 , H01L27/0886 , H01L29/0665 , H01L29/16 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/785
Abstract: A semiconductor device includes a semiconductor substrate. A first fin extends in a first direction. A first nano sheet structure includes at least two first nano sheets which extend in the first direction parallel to an upper surface of the first fin. A second fin extends in the first direction. A second nano sheet structure includes at least two second nano sheets which extend in the first direction parallel to an upper surface of the second fin. At least one of the at least two first nano sheets has a different thickness from at least one of the at least two second nano sheets.
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公开(公告)号:US09240461B2
公开(公告)日:2016-01-19
申请号:US13932047
申请日:2013-07-01
Applicant: Samsung Electronics Co., Ltd.
Inventor: Seok-Hoon Kim , Dong-Chan Suh , Byeong-Chan Lee
IPC: H01L21/768 , H01L29/66 , H01L21/764 , H01L29/78 , H01L29/165 , H01L29/49 , H01L29/51
CPC classification number: H01L29/6656 , H01L21/764 , H01L21/7682 , H01L29/165 , H01L29/4966 , H01L29/517 , H01L29/6653 , H01L29/66545 , H01L29/66636 , H01L29/7848
Abstract: A method for fabricating a semiconductor device comprises forming a dummy gate pattern and a spacer that is arranged on a sidewall of the dummy gate pattern on a substrate, forming an air gap on both sides of the dummy gate pattern by removing the spacer, exposing the substrate by removing the dummy gate pattern, and sequentially forming a gate insulating film including a high-k insulating film and a metal gate electrode on the exposed substrate.
Abstract translation: 一种半导体器件的制造方法,其特征在于,在基板上形成伪栅极图案和间隔物,该间隔物配置在伪栅极图案的侧壁上,通过去除间隔物,在伪栅极图案的两面形成气隙, 通过去除伪栅极图案,并且在暴露的基板上顺序地形成包括高k绝缘膜和金属栅电极的栅极绝缘膜。
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公开(公告)号:US11069685B2
公开(公告)日:2021-07-20
申请号:US16453721
申请日:2019-06-26
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Dong-Chan Suh , Gi-Gwan Park , Dong-Woo Kim , Dong-Suk Shin
IPC: H01L27/092 , H01L21/8238 , H01L29/165 , H01L29/66 , H01L29/04 , H01L29/06 , H01L29/423 , H01L29/786
Abstract: A semiconductor device includes a substrate including a first region and a second region, fin type active areas extending in a first direction away from the substrate in each of the first and second regions, a plurality of nanosheets extending parallel to an upper surface of the fin type active areas and being spaced apart from the upper surface of the fin type active areas, a gate extending over the fin type active areas in a second direction crossing the first direction, a gate dielectric layer interposed between the gate and each of the nanosheets, first source and drain regions included in the first region and second source and drain regions included in the second region, and insulating spacers interposed between the fin type active areas and the nanosheets, wherein air spacers are interposed between the insulating spacers and the first source and drain regions.
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公开(公告)号:US09608117B2
公开(公告)日:2017-03-28
申请号:US15049859
申请日:2016-02-22
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jin-Bum Kim , Nam Kyu Kim , Hyun-Ho Noh , Dong-Chan Suh , Byeong-Chan Lee , Su-Jin Jung , Jin-Yeong Joe , Bon-Young Koo
CPC classification number: H01L29/785 , H01L29/0649 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/7848 , H01L29/7856
Abstract: A semiconductor device includes an active fin structure extending in a first direction, the active fin structure including protruding portions divided by a recess, a plurality of gate structures extending in a second direction crossing the first direction and covering the protruding portions of the active fin structure, a first epitaxial pattern in a lower portion of the recess between the gate structures, a second epitaxial pattern on a portion of the first epitaxial pattern, the second epitaxial pattern contacting a sidewall of the recess, and a third epitaxial pattern on the first and second epitaxial patterns, the third epitaxial pattern filling the recess. The first epitaxial pattern includes a first impurity region having a first doping concentration, the second epitaxial pattern includes a second impurity region having a second doping concentration lower than the a first doping concentration, and the third epitaxial pattern includes a third impurity region having a third doping concentration higher than the second doping concentration. The semiconductor device may have good electrical characteristics.
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