公开(公告)号：US09275995B2

公开(公告)日：2016-03-01

申请号：US14543140

申请日：2014-11-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Bum Kim ,  Bon-Young Koo ,  Seok-Hoon Kim ,  Chul Kim ,  Kwan-Heum Lee ,  Byeong-Chan Lee ,  Su-Jin Jung

IPC: H01L27/088 ,  H01L29/161 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L29/0653 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/785

Abstract: An integrated circuit device includes an electrically conductive pattern on a substrate. This electrically conductive pattern may be a gate pattern of a field effect transistor. A first electrically insulating spacer is provided on a sidewall of the electrically conductive pattern. The first electrically insulating spacer includes a first lower spacer and a first upper spacer, which extends on the first lower spacer and has a side surface vertically aligned with a corresponding side surface of the first lower spacer. The first upper spacer has a greater dielectric constant relative to a dielectric constant of the first lower spacer. A pair of parallel channel regions may also be provided, which protrude from a surface of the substrate. The electrically conductive pattern may surround top and side surfaces of the pair of parallel channel regions.

Abstract translation: 集成电路器件包括在衬底上的导电图案。 该导电图案可以是场效应晶体管的栅极图案。 第一电绝缘垫片设置在导电图案的侧壁上。 第一电绝缘间隔件包括第一下间隔件和第一上间隔件，其在第一下间隔件上延伸并且具有与第一下间隔件的对应侧表面垂直对准的侧表面。 第一上间隔物相对于第一下间隔物的介电常数具有更大的介电常数。 还可以设置一对平行的通道区域，其从衬底的表面突出。 导电图案可以围绕该对平行通道区域的顶表面和侧表面。

公开(公告)号：US10147723B2

公开(公告)日：2018-12-04

申请号：US15653733

申请日：2017-07-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok-Hoon Kim ,  Jin-Bum Kim ,  Kwan-Heum Lee ,  Byeong-Chan Lee ,  Cho-Eun Lee ,  Jin-Hee Han ,  Bon-Young Koo

IPC: H01L27/088 ,  H01L27/02 ,  H01L29/78 ,  H01L27/11 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417

Abstract: A semiconductor device includes a substrate, a first active fin and a second active fin on the substrate, respectively, a plurality of first epitaxial layers on the first active fin and on the second active fin, respectively, a plurality of second epitaxial layers on the plurality of first epitaxial layers, a bridge layer connecting the plurality of second epitaxial layers to each other, and a third epitaxial layer on the bridge layer.

公开(公告)号：US09306054B2

公开(公告)日：2016-04-05

申请号：US13901653

申请日：2013-05-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-Bum Kim

IPC: H01L29/78 ,  H01L21/28 ,  H01L27/092 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/285 ,  H01L29/49 ,  H01L29/51 ,  H01L29/165

CPC classification number: H01L29/78 ,  H01L21/28008 ,  H01L21/28518 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method of fabricating a semiconductor device is provided. A plurality of first gate electrode structure is formed on a substrate. A recess is formed in the substrate, wherein the recess is formed between two adjacent first gate electrode structures of the plurality of first gate electrode structure. A diffusion prevention layer includes a first material and is formed on the recess of the substrate. A first pre-silicide layer includes a second material different from the first material and is formed on the diffusion prevention layer. A metal layer is formed on the first pre-silicide layer. The first pre-silicide layer and the metal layer are changed to a first silicide layer by performing an annealing process to the substrate. The diffusion prevention layer prevents metal atoms of the metal layer from diffusing to the substrate, and the first silicide layer comprises a monocrystalline layer.

Abstract translation: 提供一种制造半导体器件的方法。 在基板上形成多个第一栅电极结构。 在衬底中形成凹部，其中凹部形成在多个第一栅电极结构的两个相邻的第一栅电极结构之间。 扩散防止层包括第一材料并且形成在基板的凹部上。 第一预硅化物层包括与第一材料不同的第二材料，并形成在扩散防止层上。 在第一预硅化物层上形成金属层。 通过对衬底进行退火处理，将第一预硅化物层和金属层改变为第一硅化物层。 扩散防止层防止金属层的金属原子扩散到基板，并且第一硅化物层包括单晶层。

公开(公告)号：US20160284703A1

公开(公告)日：2016-09-29

申请号：US15177421

申请日：2016-06-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok-Hoon Kim ,  Jin-Bum Kim ,  Kwan-Heum Lee ,  Byeong-Chan Lee ,  Cho-Eun Lee ,  Jin-Hee Han ,  Bon-Young Koo

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/092

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/78 ,  H01L29/7842 ,  H01L29/7849 ,  H01L29/785

Abstract: A semiconductor device includes a substrate, a first active fin and a second active fin on the substrate, respectively, a plurality of first epitaxial layers on the first active fin and on the second active fin, respectively, a plurality of second epitaxial layers on the plurality of first epitaxial layers, a bridge layer connecting the plurality of second epitaxial layers to each other, and a third epitaxial layer on the bridge layer.

公开(公告)号：US09054217B2

公开(公告)日：2015-06-09

申请号：US14029326

申请日：2013-09-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-Bum Kim

IPC: H01L21/8238 ,  H01L21/28 ,  H01L29/66 ,  H01L21/033

CPC classification number: H01L21/8238 ,  H01L21/0334 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66477 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636

Abstract: A method for fabricating a semiconductor device is provided. A first gate pattern and a second gate pattern are adjacent to each other and are formed on an active region of a substrate. The active region is defined by an isolation film. A first recess is formed between the first gate pattern and the second gate pattern. A first sacrificial film pattern is formed on a bottom surface of the first recess using a directional deposition process. A second recess is formed by etching the first recess using the first sacrificial film pattern as a etch mask. The first recess is laterally extended to form the second recess.

Abstract translation: 提供一种制造半导体器件的方法。 第一栅极图案和第二栅极图案彼此相邻并且形成在衬底的有源区域上。 有源区由隔离膜定义。 在第一栅极图案和第二栅极图案之间形成第一凹部。 使用定向沉积工艺在第一凹部的底表面上形成第一牺牲膜图案。 通过使用第一牺牲膜图案作为蚀刻掩模蚀刻第一凹部来形成第二凹部。 第一凹槽横向延伸以形成第二凹槽。

公开(公告)号：US09054189B1

公开(公告)日：2015-06-09

申请号：US14148110

申请日：2014-01-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-Bum Kim ,  Taek-Soo Jeon

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device is provided. An active fin protrudes from a substrate. A gate structure is formed on the substrate and the active fin. The gate structure extends in a first direction. The gate structure crosses a first region of the active fin in a second direction. A first epitaxial layer is formed on a second region of the active fin. The second region of the active fin is not covered with the gate structure. A second epitaxial layer is formed on the first epitaxial layer, the second epitaxial layer including an impurity. The first epitaxial layer includes a blocking material. The blocking material of the first epitaxial layer prevents the impurity of the second epitaxial layer from passing through the first epitaxial layer to block diffusion of the impurity to a channel region formed in the first region of the active fin.

Abstract translation: 提供半导体器件。 活性翅片从基底突出。 栅极结构形成在衬底和活性鳍上。 栅极结构沿第一方向延伸。 栅极结构沿着第二方向跨越有源鳍片的第一区域。 在活性鳍片的第二区域上形成第一外延层。 活动鳍片的第二区域不被栅极结构覆盖。 在第一外延层上形成第二外延层，第二外延层包括杂质。 第一外延层包括阻挡材料。 第一外延层的阻挡材料防止第二外延层的杂质通过第一外延层，以阻止杂质扩散到形成在活性鳍片的第一区域中的沟道区域。

公开(公告)号：US20150011070A1

公开(公告)日：2015-01-08

申请号：US13934369

申请日：2013-07-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-Bum Kim ,  Kyung-Bum Koo ,  Taek-Soo Jeon ,  Tae-Ho Cha ,  Judson R. Holt ,  Henry K. Utomo

IPC: H01L29/66

CPC classification number: H01L29/66636 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7848

Abstract: A gate pattern is formed on a first region of a substrate. An epitaxial layer is formed on a second region of the substrate. A recess is formed in the second region of the substrate by etching the epitaxial layer and the substrate underneath. The first region is adjacent to the second region.

Abstract translation: 在衬底的第一区域上形成栅极图案。 在衬底的第二区域上形成外延层。 通过在其下方蚀刻外延层和衬底，在衬底的第二区域中形成凹部。 第一区域与第二区域相邻。

公开(公告)号：US08921940B2

公开(公告)日：2014-12-30

申请号：US13839870

申请日：2013-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Bum Kim ,  Suk-Hun Choi

IPC: H01L29/66 ,  H01L27/12 ,  H01L21/76

CPC classification number: H01L21/76 ,  H01L21/76224 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: To fabricate a semiconductor device, a fin is formed to protrude from a substrate. The fin is extended in a first direction. A gate line is formed on the fin and the substrate. The gate line is extended in a second direction crossing the first direction. An amorphous material layer is conformally formed to cover the substrate, the fin, and the gate line. The amorphous material layer is partially removed, thereby forming a first remaining amorphous layer on side walls of the fin and a second remaining amorphous layer on side walls of the gate line. The first remaining amorphous layer and the second remaining amorphous layer are annealed and the first remaining amorphous material layer and the second remaining amorphous material layer are crystallized into a monocrystalline material layer and a polycrystalline material layer, respectively. The polycrystalline material layer is removed.

Abstract translation: 为了制造半导体器件，形成从基板突出的翅片。 翅片沿第一个方向延伸。 在翅片和基板上形成栅极线。 栅极线在与第一方向交叉的第二方向上延伸。 保形地形成无定形材料层以覆盖基板，翅片和栅极线。 部分去除非晶材料层，从而在翅片的侧壁上形成第一剩余非晶层，在栅极线的侧壁上形成第二剩余非晶层。 第一剩余非晶层和第二剩余非晶层退火，并且第一剩余非晶态材料层和第二剩余非晶态材料层分别结晶成单晶材料层和多晶材料层。 去除多晶材料层。

公开(公告)号：US11469237B2

公开(公告)日：2022-10-11

申请号：US16388347

申请日：2019-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Bum Kim ,  Myung-Gil Kang ,  Kang-Hun Moon ,  Cho-Eun Lee ,  Su-Jin Jung ,  Min-Hee Choi ,  Yang Xu ,  Dong-Suk Shin ,  Kwan-Heum Lee ,  Hoi-Sung Chung

IPC: H01L27/088 ,  H01L27/11 ,  H01L29/66 ,  H01L29/78 ,  H01L23/485 ,  H01L21/8234 ,  H01L29/417 ,  H01L23/528 ,  H01L29/08 ,  H01L29/161 ,  H01L29/45 ,  H01L27/092 ,  H01L29/165

Abstract: A semiconductor device may include a first active fin, a plurality of second active fins, a first source/drain layer structure, and a second source/drain layer structure. The first active fin may be on a first region of a substrate. The second active fins may be on a second region of the substrate. The first and second gate structures may be on the first and second active fins, respectively. The first source/drain layer structure may be on a portion of the first active fin that is adjacent to the first gate structure. The second source/drain layer structure may commonly contact upper surfaces of the second active fins adjacent to the second gate structure. A top surface of the second source/drain layer structure may be further from the surface of the substrate than a top surface of the first source/drain layer structure is to the surface of the substrate.

公开(公告)号：US20190244963A1

公开(公告)日：2019-08-08

申请号：US16388347

申请日：2019-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Bum Kim ,  Myung-Gil Kang ,  Kang-Hun Moon ,  Cho-Eun Lee ,  Su-Jin Jung ,  Min-Hee Choi ,  Yang Xu ,  Dong-Suk Shin ,  Kwan-Heum Lee ,  Hoi-Sung Chung

IPC: H01L27/11 ,  H01L29/66 ,  H01L29/161 ,  H01L29/78 ,  H01L29/08 ,  H01L23/528 ,  H01L29/417 ,  H01L21/8234 ,  H01L27/088 ,  H01L23/485 ,  H01L29/45

CPC classification number: H01L27/1104 ,  H01L21/823431 ,  H01L23/485 ,  H01L23/5283 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/456 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device may include a first active fin, a plurality of second active fins, a first source/drain layer structure, and a second source/drain layer structure. The first active fin may be on a first region of a substrate. The second active fins may be on a second region of the substrate. The first and second gate structures may be on the first and second active fins, respectively. The first source/drain layer structure may be on a portion of the first active fin that is adjacent to the first gate structure. The second source/drain layer structure may commonly contact upper surfaces of the second active fins adjacent to the second gate structure. A top surface of the second source/drain layer structure may be further from the surface of the substrate than a top surface of the first source/drain layer structure is to the surface of the substrate.