Abstract:
A semiconductor device includes a first semiconductor chip at least partially overlapping a second semiconductor chip. The first semiconductor chip is coupled to a substrate and has a first width, and the second semiconductor chip has a second width. The device also includes a heat sink coupled to the second semiconductor chip and having a third width different from at least one of the first width or the second width. A package molding section at least partially overlaps a first area of the heat sink and does not overlap a second area of the heat sink which includes a top surface of the heat sink.
Abstract:
A semiconductor package includes a substrate. A first semiconductor chip is disposed on the substrate and is electrically connected to the substrate. The first semiconductor chip comprises a first sidewall extending in a first direction, a second sidewall extending in a second direction that crosses the first direction, and a third sidewall disposed between the first sidewall and the second sidewall and configured to connect the first sidewall and the second side wall. The third sidewall has a curved surface shape. A second semiconductor chip is disposed on the first semiconductor chip and is electrically connected to the first semiconductor chip.
Abstract:
A semiconductor package includes a heat spreader. The semiconductor package includes a substrate, a first semiconductor chip disposed on the substrate, and a second semiconductor chip disposed on the first semiconductor chip. The heat spreader may be formed on the first semiconductor chip. A thermal interfacial material (TIM) layer may be formed to be in contact with the first semiconductor chip and the heat spreader and may cover side surfaces of the second semiconductor chip. Heat generated by the first semiconductor chip may be emitted through the TIM layer and the heat spreader. Thermal stress caused by a difference in coefficients of thermal expansion (CTEs) between the substrate and the first semiconductor chip may be distributed to ensure structural stability.
Abstract:
A semiconductor package includes a first semiconductor chip, a second semiconductor chip and a sealing member. The first semiconductor chip includes a substrate having a first surface and a second surface opposite to the first surface and having an opening that extends in a predetermined depth from the second surface, and a plurality of through electrodes extending in a thickness direction from the first surface, end portions of the through electrodes being exposed through a bottom surface of the opening. The second semiconductor chip is received in the opening and mounted on the bottom surface of the opening. The sealing member covers the second semiconductor chip in the opening.