公开(公告)号：US09184136B2

公开(公告)日：2015-11-10

申请号：US14141947

申请日：2013-12-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiyoung Kim ,  Daeik Kim ,  Kang-Uk Kim ,  Nara Kim ,  Jemin Park ,  Kyuhyun Lee ,  Hyun-Woo Chung ,  Gyoyoung Jin ,  HyeongSun Hong ,  Yoosang Hwang

IPC: H01L23/544 ,  H01L23/48 ,  H01L21/683 ,  H01L27/06 ,  H01L27/146 ,  H01L21/768 ,  H01L27/108

CPC classification number: H01L23/544 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L27/0688 ,  H01L27/10897 ,  H01L27/14632 ,  H01L27/14634 ,  H01L27/1464 ,  H01L2221/68327 ,  H01L2221/6835 ,  H01L2221/68363 ,  H01L2223/54426 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating a semiconductor device includes providing a semiconductor substrate having a first surface and a second surface opposite the first surface, forming an alignment key and a connection contact that penetrate a portion of the semiconductor substrate and extend from the first surface toward the second surface, forming a first circuit on the first surface of the semiconductor substrate such that the first circuit is electrically connected to the connection contact, recessing the second surface of the semiconductor substrate to form a third surface exposing the alignment key and the connection contact, and forming a second circuit on the third surface of the semiconductor substrate such that the second circuit is electrically connected to the connection contact.

Abstract translation: 一种制造半导体器件的方法包括提供具有第一表面和与第一表面相对的第二表面的半导体衬底，形成对准键和穿过半导体衬底的一部分并从第一表面延伸到第二表面的连接触点 在所述半导体衬底的所述第一表面上形成第一电路，使得所述第一电路电连接到所述连接触点，使所述半导体衬底的所述第二表面凹陷以形成暴露所述对准键和所述连接触点的第三表面，以及 在半导体衬底的第三表面上形成第二电路，使得第二电路电连接到连接触点。

公开(公告)号：US09449677B2

公开(公告)日：2016-09-20

申请号：US14537387

申请日：2014-11-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiyoung Kim ,  Yongchul Oh ,  Dongsoo Woo ,  Hyun-Woo Chung ,  Gyoyoung Jin ,  Sungkwan Choi ,  Hyeongsun Hong ,  Yoosang Hwang

IPC: G11C11/40 ,  G11C11/4096 ,  H01L27/108 ,  G11C11/404 ,  G11C11/408 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

CPC classification number: G11C11/4096 ,  G11C11/404 ,  G11C11/4085 ,  H01L21/823437 ,  H01L27/10823 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10891 ,  H01L27/10894 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/66484 ,  H01L29/66613 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7831

Abstract: A semiconductor device may include a semiconductor substrate with first and second spaced apart source/drain regions defining a channel region therebetween and a control gate structure on the channel region between the first and second spaced apart source/drain regions. More particularly, the control gate structure may include a first gate electrode on the channel region adjacent the first source/drain region, and a second gate electrode on the channel region adjacent the second source/drain region. Moreover, the first and second gate electrodes may be electrically isolated. Related devices, structures, methods of operation, and methods of fabrication are also discussed.

Abstract translation: 半导体器件可以包括具有限定其间的沟道区的第一和第二间隔开的源极/漏极区的半导体衬底，以及在第一和第二间隔开的源极/漏极区之间的沟道区上的控制栅极结构。 更具体地，控制栅极结构可以包括在与第一源极/漏极区域相邻的沟道区域上的第一栅极电极以及与第二源极/漏极区域相邻的沟道区域上的第二栅极电极。 此外，第一和第二栅电极可以是电隔离的。 还讨论了相关设备，结构，操作方法和制造方法。