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公开(公告)号:US20200251527A1
公开(公告)日:2020-08-06
申请号:US16512627
申请日:2019-07-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Hee-Ju Shin , Ung-Hwan PI
Abstract: An MRAM device includes a first conductive pattern including a material generating a spin orbital torque, a torque transfer pattern contacting a portion of an upper surface of the first conductive pattern, an insulation pattern on a side of the torque transfer pattern and covering the first conductive pattern, and a magnetic tunnel junction (MTJ) structure on the torque transfer pattern, the MTJ structure including a free layer pattern, a tunnel barrier pattern, and a fixed layer pattern sequentially stacked.
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公开(公告)号:US11004900B2
公开(公告)日:2021-05-11
申请号:US16512627
申请日:2019-07-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Hee-Ju Shin , Ung-Hwan Pi
Abstract: An MRAM device includes a first conductive pattern including a material generating a spin orbital torque, a torque transfer pattern contacting a portion of an upper surface of the first conductive pattern, an insulation pattern on a side of the torque transfer pattern and covering the first conductive pattern, and a magnetic tunnel junction (MTJ) structure on the torque transfer pattern, the MTJ structure including a free layer pattern, a tunnel barrier pattern, and a fixed layer pattern sequentially stacked.
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公开(公告)号:US09666789B2
公开(公告)日:2017-05-30
申请号:US14741446
申请日:2015-06-16
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jeong-Heon Park , Ki-Woong Kim , Hee-Ju Shin , Joon-Myoung Lee , Woo-Jin Kim , Jae-Hoon Kim , Se-Chung Oh , Yun-Jae Lee
CPC classification number: H01L43/02 , G11C11/161 , H01F10/30 , H01F10/32 , H01F10/3254 , H01F10/3272 , H01L23/528 , H01L27/222 , H01L43/08 , H01L2924/0002 , H01L2924/00
Abstract: A semiconductor device is provided having a free layer and a pinned layer spaced apart from each other. A tunnel barrier layer is formed between the free layer and the pinned layer. The pinned layer may include a lower pinned layer, and an upper pinned layer spaced apart from the lower pinned layer. A spacer may be formed between the lower pinned layer and the upper pinned layer. A non-magnetic junction layer may be disposed adjacent to the spacer or between layers in the upper or lower pinned layer.
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