公开(公告)号：US10109676B2

公开(公告)日：2018-10-23

申请号：US15293771

申请日：2016-10-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Hoon Bak ,  Woo-Jin Kim ,  Mina Lee ,  Gwan-Hyeob Koh ,  Yoon-Jong Song

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  G11C11/16 ,  H01L43/10

Abstract: A magnetic tunnel junction (MTJ) structure includes a fixed layer pattern structure having a perpendicular magnetization direction, a tunnel barrier pattern on the fixed layer pattern structure, a free layer pattern on the tunnel barrier pattern, the free layer pattern having a perpendicular magnetization direction, a first surface magnetism induction pattern on the free layer pattern, the first surface magnetism induction pattern inducing a perpendicular magnetism in a surface of the free layer pattern, a conductive pattern on the first surface magnetism induction pattern, and a ferromagnetic pattern on the conductive pattern.

公开(公告)号：US10714678B2

公开(公告)日：2020-07-14

申请号：US16727986

申请日：2019-12-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Sung Park ,  Woo-Jin Kim ,  Jeong-Heon Park ,  Se-Chung Oh ,  Joon-Myoung Lee ,  Hyun Cho

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/10 ,  H01L43/12

Abstract: The methods of manufacturing an MRAM device and MRAM devices are provided. The methods may include forming a first electrode on an upper surface of a substrate, forming a first magnetic layer on the first electrode, forming a tunnel barrier structure on the first magnetic layer, forming a second magnetic layer on the tunnel barrier structure, and forming a second electrode on the second magnetic layer. The tunnel barrier structure may include a first tunnel barrier layer and a second tunnel barrier layer that are sequentially stacked on the first magnetic layer and may have different resistivity distributions from each other along a horizontal direction that may be parallel to the upper surface of the substrate.

公开(公告)号：US20190102332A1

公开(公告)日：2019-04-04

申请号：US15943647

申请日：2018-04-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joon-Woo Cho ,  Yun Ju Kwon ,  Sang Woo Kim ,  Woo-Jin Kim

IPC: G06F13/362 ,  G06F13/16 ,  G06F13/10

Abstract: A bus system is provided. A bus system includes a slave functional block and a master functional block. The master functional block transmits a first command to the slave functional block. The slave functional block includes a first bus protector. The first bus protector receives the first command on behalf of the slave functional block and transmits a dummy signal corresponding to the first command to the master functional block in response to the slave functional block being in a state of not being able to receive the first command or not being able to transmit a response signal corresponding to the first command.

公开(公告)号：US09666789B2

公开(公告)日：2017-05-30

申请号：US14741446

申请日：2015-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeong-Heon Park ,  Ki-Woong Kim ,  Hee-Ju Shin ,  Joon-Myoung Lee ,  Woo-Jin Kim ,  Jae-Hoon Kim ,  Se-Chung Oh ,  Yun-Jae Lee

IPC: H01L43/02 ,  H01F10/32 ,  H01L43/08 ,  G11C11/16 ,  H01L23/528 ,  H01L27/22 ,  H01F10/30

CPC classification number: H01L43/02 ,  G11C11/161 ,  H01F10/30 ,  H01F10/32 ,  H01F10/3254 ,  H01F10/3272 ,  H01L23/528 ,  H01L27/222 ,  H01L43/08 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device is provided having a free layer and a pinned layer spaced apart from each other. A tunnel barrier layer is formed between the free layer and the pinned layer. The pinned layer may include a lower pinned layer, and an upper pinned layer spaced apart from the lower pinned layer. A spacer may be formed between the lower pinned layer and the upper pinned layer. A non-magnetic junction layer may be disposed adjacent to the spacer or between layers in the upper or lower pinned layer.

公开(公告)号：US11665970B2

公开(公告)日：2023-05-30

申请号：US17337768

申请日：2021-06-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Whan-Kyun Kim ,  Deok-Hyeon Kang ,  Woo-Jin Kim ,  Woo-Chang Lim ,  Jun-Ho Jeong

IPC: G11C11/16 ,  H01L43/12 ,  H01F41/32 ,  H01L27/22 ,  H01F10/32 ,  H01L43/02 ,  H01F41/30 ,  H01L43/08

CPC classification number: H01L43/12 ,  G11C11/161 ,  H01F10/3254 ,  H01F41/307 ,  H01F41/32 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08

Abstract: A method of manufacturing an MRAM device, the method including forming a first magnetic layer on a substrate; forming a first tunnel barrier layer on the first magnetic layer such that the first tunnel barrier layer includes a first metal oxide, the first metal oxide being formed by oxidizing a first metal layer at a first temperature; forming a second tunnel barrier layer on the first tunnel barrier layer such that the second tunnel barrier layer includes a second metal oxide, the second metal oxide being formed by oxidizing a second metal layer at a second temperature that is greater than the first temperature; and forming a second magnetic layer on the second tunnel barrier layer.

公开(公告)号：US10423553B2

公开(公告)日：2019-09-24

申请号：US15996477

申请日：2018-06-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woo-Jin Kim ,  Nak-Hee Seong ,  Hee-Seong Lee

IPC: G06F13/364 ,  G06F13/42 ,  G06F13/40

Abstract: A system-on-chip (SoC) may include a master, a slave, and an asynchronous interface having a first first-in first-out (FIFO) memory connected to the master and the slave. A write operation of the FIFO memory is controlled based upon a comparison of a write pointer and an expected write pointer of the FIFO memory, and a read operation of the FIFO memory is controlled based upon a comparison of a read pointer and an expected read pointer of the FIFO.

公开(公告)号：US10784442B2

公开(公告)日：2020-09-22

申请号：US16114638

申请日：2018-08-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Whan-Kyun Kim ,  Deok-Hyeon Kang ,  Woo-Jin Kim ,  Woo-Chang Lim ,  Jun-Ho Jeong

IPC: H01L43/12 ,  G11C11/16 ,  H01F41/32 ,  H01L27/22 ,  H01F10/32 ,  H01L43/02 ,  H01F41/30

Abstract: A method of manufacturing an MRAM device, the method including forming a first magnetic layer on a substrate; forming a first tunnel barrier layer on the first magnetic layer such that the first tunnel barrier layer includes a first metal oxide, the first metal oxide being formed by oxidizing a first metal layer at a first temperature; forming a second tunnel barrier layer on the first tunnel barrier layer such that the second tunnel barrier layer includes a second metal oxide, the second metal oxide being formed by oxidizing a second metal layer at a second temperature that is greater than the first temperature; and forming a second magnetic layer on the second tunnel barrier layer.

公开(公告)号：US10769085B2

公开(公告)日：2020-09-08

申请号：US15943647

申请日：2018-04-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joon-Woo Cho ,  Yun Ju Kwon ,  Sang Woo Kim ,  Woo-Jin Kim

IPC: G06F11/07 ,  G06F13/362 ,  G06F13/16 ,  G06F13/10 ,  G06F11/30

Abstract: A bus system is provided. A bus system includes a slave functional block and a master functional block. The master functional block transmits a first command to the slave functional block. The slave functional block includes a first bus protector. The first bus protector receives the first command on behalf of the slave functional block and transmits a dummy signal corresponding to the first command to the master functional block in response to the slave functional block being in a state of not being able to receive the first command or not being able to transmit a response signal corresponding to the first command.

公开(公告)号：US10559746B2

公开(公告)日：2020-02-11

申请号：US16108192

申请日：2018-08-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Sung Park ,  Woo-Jin Kim ,  Jeong-Heon Park ,  Se-Chung Oh ,  Joon-Myoung Lee ,  Hyun Cho

IPC: H01L43/12 ,  H01L43/02 ,  H01L27/22 ,  H01L43/10

Abstract: The methods of manufacturing an MRAM device and MRAM devices are provided. The methods may include forming a first electrode on an upper surface of a substrate, forming a first magnetic layer on the first electrode, forming a tunnel barrier structure on the first magnetic layer, forming a second magnetic layer on the tunnel barrier structure, and forming a second electrode on the second magnetic layer. The tunnel barrier structure may include a first tunnel barrier layer and a second tunnel barrier layer that are sequentially stacked on the first magnetic layer and may have different resistivity distributions from each other along a horizontal direction that may be parallel to the upper surface of the substrate.

公开(公告)号：US10193060B2

公开(公告)日：2019-01-29

申请号：US15449538

申请日：2017-03-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoon-Sung Han ,  Ki-Seok Suh ,  Woo-Jin Kim

IPC: H01L43/08 ,  H01L27/22 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

Abstract: An MRAM device may include an insulating interlayer structure, a lower electrode contact structure and a variable resistance structure. The insulating interlayer may be formed on a substrate. The lower electrode contact structure may extend through the insulating interlayer. The lower electrode contact structure may include a first electrode having a pillar shape and a second electrode having a cylindrical shape on the first electrode. An upper surface of the second electrode may have a ring shape. A variable resistance structure may be formed on the second electrode. The variable resistance structure may include a lower electrode, a magnetic tunnel junction (MTJ) structure and an upper electrode sequentially stacked.