Abstract:
An image sensor includes a pixel array including a first pixel and a second pixel which are connected to a first column line, and a row driver configured to control a read operation of the second pixel. A voltage of the first column line is determined based on a higher voltage among a voltage of a floating diffusion node of the first pixel and a voltage of a floating diffusion node of the second pixel during the read operation of the second pixel.
Abstract:
An image sensor includes a pixel array including a first pixel and a second pixel which are connected to a first column line, and a row driver configured to control a read operation of the second pixel. A voltage of the first column line is determined based on a higher voltage among a voltage of a floating diffusion node of the first pixel and a voltage of a floating diffusion node of the second pixel during the read operation of the second pixel.
Abstract:
A signal transfer circuit includes a transmission circuit, a conversion circuit and a sensing output circuit. The transmission circuit outputs a driving signal to a signal line. The conversion circuit receives an input signal that is a single-ended signal transferred through the signal line and converts the input signal to a differential signal including a first output amplified signal and a second output amplified signal. The first output amplified signal swings downwardly from a first output DC level and the second output amplified signal swings upwardly from a second output DC level that is lower than the first output DC level. The sensing output circuit generates an output signal based on the differential signal. The number of the signal lines is reduced without decrease in performance of signal transfer, and sizes of the signal transfer circuit and the device including the signal transfer circuit are reduced.
Abstract:
An image sensor includes a pixel array including a pixel array comprising a first pixel and a second pixel which are electrically connected to a first column line, a row driver configured to receive a clamp voltage and a selection voltage, select the first pixel based on the clamp voltage and select the second pixel based on the selection voltage. A voltage of the first column line is determined based on a higher voltage among a first output voltage of the first pixel and a second output voltage of the second pixel during a read operation of the second pixel.
Abstract:
An image sensor includes a pixel array, a plurality of comparators, a plurality of counters and a plurality of synchronization circuits. The pixel array includes a plurality of pixels configured to generate analog signals by sensing incident light. The comparators generate comparison signals by comparing the analog signals with a reference signal. The counters are grouped into a plurality of counter groups. Each of the counters generates digital signals corresponding to the analog signals by counting, the counting terminated by the comparison signals. Each of the synchronization circuits synchronizes input clock signals to a source clock signal to provide synchronized input clock signals to each of the counter groups.
Abstract:
A binary-to-Gray converting circuit includes a buffer unit and a conversion unit. The buffer unit generates a data code of n bits in response to a power supply voltage and a second binary bit signal through an nth binary bit signal except for a first binary bit signal corresponding to a least significant bit of a binary code of n bits. The conversion unit generates a Gray code of n bits based on the binary code and the data code, and generates a kth Gray bit signal of the Gray code by latching a kth data bit signal of the data code in response to a kth binary bit signal of the binary code. A logic level of the kth Gray bit signal is determined corresponding to a logic level of the kth data bit signal.
Abstract:
An image sensor includes a pixel array including a plurality of pixels, an analog-to-digital converter having a first counter for converting an analog signal into a digital signal, and an output buffer having a first memory. A first counter test result value generated as a test result for the first counter is stored in the first memory in a test mode. The output buffer outputs the first counter test result value from the first memory to an outside of the output buffer in response to a first selection signal. The output buffer further includes a reset logic circuit for resetting the first memory depending on whether the first counter test result value is output or not. The plurality of pixels generate the analog signal in response to incident light.
Abstract:
An image sensor includes a pixel array including a plurality of pixels, an analog-to-digital converter having a first counter for converting an analog signal into a digital signal, and an output buffer having a first memory. A first counter test result value generated as a test result for the first counter is stored in the first memory in a test mode. The output buffer outputs the first counter test result value from the first memory to an outside of the output buffer in response to a first selection signal. The output buffer further includes a reset logic circuit for resetting the first memory depending on whether the first counter test result value is output or not. The plurality of pixels generate the analog signal in response to incident light.
Abstract:
A binary-to-Gray converting circuit includes a buffer unit and a conversion unit. The buffer unit generates a data code of n bits in response to a power supply voltage and a second binary bit signal through an nth binary bit signal except for a first binary bit signal corresponding to a least significant bit of a binary code of n bits. The conversion unit generates a Gray code of n bits based on the binary code and the data code, and generates a kth Gray bit signal of the Gray code by latching a kth data bit signal of the data code in response to a kth binary bit signal of the binary code. A logic level of the kth Gray bit signal is determined corresponding to a logic level of the kth data bit signal.