公开(公告)号：US09397196B2

公开(公告)日：2016-07-19

申请号：US14699091

申请日：2015-04-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Jun Sim ,  Jae-Young Park ,  Sun-Young Lee

IPC: H01L21/428 ,  H01L29/66 ,  H01L21/306 ,  H01L21/762 ,  H01L21/28 ,  H01L29/51 ,  H01L21/02 ,  H01L21/268

CPC classification number: H01L29/66795 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/0234 ,  H01L21/02351 ,  H01L21/2686 ,  H01L21/28185 ,  H01L21/30604 ,  H01L21/76224 ,  H01L29/165 ,  H01L29/51 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: In a method of manufacturing a semiconductor device, a preliminary gate insulation layer is formed on a substrate, and at least a portion of the substrate serves as a channel region. A hydrogen plasma treatment is performed on the preliminary gate insulation layer to form a gate insulation layer, and the hydrogen plasma treatment supplying a hydrogen-containing gas and an inert gas supply in a chamber via different gas supply parts to form a hydrogen plasma region and an inert gas plasma region in the chamber, respectively. A gate electrode is formed on the gate insulation layer, and impurity regions are formed at upper portions of the substrate adjacent to the gate electrode.

Abstract translation: 在半导体装置的制造方法中，在基板上形成预备栅极绝缘层，并且至少一部分基板作为沟道区域。 在预备栅极绝缘层上进行氢等离子体处理以形成栅极绝缘层，并且氢等离子体处理通过不同的气体供应部分在室中提供含氢气体和惰性气体源，以形成氢等离子体区域， 室内的惰性气体等离子体区域。 栅电极形成在栅极绝缘层上，杂质区形成在与栅电极相邻的衬底的上部。

公开(公告)号：US10797160B2

公开(公告)日：2020-10-06

申请号：US16149387

申请日：2018-10-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Jun Sim ,  Won-Oh Seo ,  Sun-Jung Kim ,  Ki-Yeon Park

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/02 ,  H01L27/11 ,  H01L21/3213 ,  H01L29/49

Abstract: A method of fabricating a semiconductor device may include forming a fin structure on a substrate; forming an interface film having a first thickness on the fin structure using a first process; forming a gate dielectric film having a second thickness on the interface film using a second process different from the first process; and densifying the gate dielectric film using a third process different from the first and second processes. The second thickness may be greater than the first thickness, and the first thickness of the interface film may be unchanged after the densifying of the gate dielectric film.

公开(公告)号：US10043806B2

公开(公告)日：2018-08-07

申请号：US15276274

申请日：2016-09-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kook-Tae Kim ,  Ho-Sung Son ,  Dong-Suk Shin ,  Hyun-Jun Sim ,  Ju-Ri Lee ,  Sung-Uk Jang

IPC: H01L29/15 ,  H01L31/0312 ,  H01L27/092 ,  H01L29/16 ,  H01L29/161 ,  H01L29/167 ,  H01L21/8238

Abstract: A dummy gate electrode layer and a dummy gate mask layer may be formed on a substrate. The dummy gate mask layer may be patterned to form a dummy gate mask so that a portion of the dummy gate electrode layer is exposed. Ions may be implanted into the exposed portion of the dummy gate electrode layer and a portion of the dummy gate electrode layer adjacent thereto by an angled ion implantation to form a growth blocking layer in the dummy gate electrode layer. The dummy gate electrode layer may be etched using the dummy gate mask as an etching mask to form a dummy gate electrode. A spacer may be formed on side surfaces of a dummy gate structure including the dummy gate electrode and the dummy gate mask. An SEG process may be performed to form an epitaxial layer.

公开(公告)号：US08698281B2

公开(公告)日：2014-04-15

申请号：US13655584

申请日：2012-10-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： In-Gyu Baek ,  Hyun-Jun Sim ,  Jin-Shi Zhao ,  Eun-Kyung Yim

IPC: H01L29/00

CPC classification number: G11C13/0007 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/003 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/78 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/1633

Abstract: A nonvolatile memory device, a method of fabricating the nonvolatile memory device and a processing system including the nonvolatile memory device. The nonvolatile memory device may include a plurality of internal electrodes that extend in a direction substantially perpendicular to a face of a substrate, a plurality of first external electrodes that extend substantially in parallel with the face of the substrate, and a plurality of second external electrodes that also extend substantially in parallel with the face of the substrate. Each first external electrode is on a first side of a respective one of the internal electrodes, and each second external electrode is on a second side of a respective one of the internal electrodes. These devices also include a plurality of variable resistors that contact the internal electrodes, the first external electrodes and the second external electrodes.

Abstract translation: 非易失性存储器件，非易失性存储器件的制造方法和包括非易失性存储器件的处理系统。 非易失性存储装置可以包括沿基板垂直于基板的方向延伸的多个内部电极，基本上平行于基板的表面延伸的多个第一外部电极和多个第二外部电极 其也基本上平行于衬底的表面延伸。 每个第一外部电极在相应的一个内部电极的第一侧上，并且每个第二外部电极在相应的一个内部电极的第二侧上。 这些器件还包括接触内部电极，第一外部电极和第二外部电极的多个可变电阻器。

公开(公告)号：US20130043453A1

公开(公告)日：2013-02-21

申请号：US13655584

申请日：2012-10-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： In-Gyu Baek ,  Hyun-Jun Sim ,  Jin-Shi Zhao ,  Eun-Kyung Yim

IPC: H01L45/00

CPC classification number: G11C13/0007 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/003 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/78 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/1633

Abstract: A nonvolatile memory device, a method of fabricating the nonvolatile memory device and a processing system including the nonvolatile memory device. The nonvolatile memory device may include a plurality of internal electrodes that extend in a direction substantially perpendicular to a face of a substrate, a plurality of first external electrodes that extend substantially in parallel with the face of the substrate, and a plurality of second external electrodes that also extend substantially in parallel with the face of the substrate. Each first external electrode is on a first side of a respective one of the internal electrodes, and each second external electrode is on a second side of a respective one of the internal electrodes. These devices also include a plurality of variable resistors that contact the internal electrodes, the first external electrodes and the second external electrodes.

Abstract translation: 非易失性存储器件，非易失性存储器件的制造方法和包括非易失性存储器件的处理系统。 非易失性存储装置可以包括沿基板垂直于基板的方向延伸的多个内部电极，基本上平行于基板的表面延伸的多个第一外部电极和多个第二外部电极 其也基本上平行于衬底的表面延伸。 每个第一外部电极在相应的一个内部电极的第一侧上，并且每个第二外部电极在相应的一个内部电极的第二侧上。 这些器件还包括接触内部电极，第一外部电极和第二外部电极的多个可变电阻器。

公开(公告)号：US10411011B2

公开(公告)日：2019-09-10

申请号：US16028080

申请日：2018-07-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kook-Tae Kim ,  Ho-Sung Son ,  Dong-Suk Shin ,  Hyun-Jun Sim ,  Ju-Ri Lee ,  Sung-Uk Jang

IPC: H01L27/092 ,  H01L29/16 ,  H01L29/167 ,  H01L29/78 ,  H01L29/161 ,  H01L29/66 ,  H01L21/8238

Abstract: A dummy gate electrode layer and a dummy gate mask layer may be formed on a substrate. The dummy gate mask layer may be patterned to form a dummy gate mask so that a portion of the dummy gate electrode layer is exposed. Ions may be implanted into the exposed portion of the dummy gate electrode layer and a portion of the dummy gate electrode layer adjacent thereto by an angled ion implantation to form a growth blocking layer in the dummy gate electrode layer. The dummy gate electrode layer may be etched using the dummy gate mask as an etching mask to form a dummy gate electrode. A spacer may be formed on side surfaces of a dummy gate structure including the dummy gate electrode and the dummy gate mask. An SEG process may be performed to form an epitaxial layer.