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公开(公告)号：US09263673B2
公开(公告)日：2016-02-16
申请号：US14609452
申请日：2015-01-30
发明人： Masayuki Terai , In-Gyu Baek
IPC分类号： H01L45/00
CPC分类号： H01L45/1253 , H01L27/2409 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/146
摘要： A resistive memory device includes a switching device disposed on a lower interconnection, a resistor element disposed on the switching device, and an upper interconnection disposed on the resistor element. The switching device includes a diode electrode, a high-concentration lower anode disposed on the diode electrode, a middle-concentration lower anode disposed on the lower high-concentration anode electrode, a common cathode disposed on the middle-concentration lower anode, a low-concentration upper anode disposed on the common cathode, and an high-concentration upper anode disposed on the low-concentration upper anode. The peak dopant concentration of the middle-concentration lower anode is at least 10 times greater than the peak dopant concentration of the low-concentration upper anode.
摘要翻译： 电阻式存储器件包括设置在下布线上的开关器件，设置在开关器件上的电阻器元件和设置在电阻器元件上的上部互连件。 开关装置包括二极管电极，设置在二极管电极上的高浓度下阳极，设置在下部高浓度阳极电极上的中等浓度下阳极，设置在中浓度下阳极上的公共阴极，低 - 设置在公共阴极上的浓缩上阳极和设置在低浓度上阳极上的高浓度上阳极。 中等浓度下阳极的峰值掺杂浓度比低浓度上阳极的峰值掺杂浓度高至少10倍。
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2.发明授权Nonvolatile memory devices that use resistance materials and internal electrodes 有权使用电阻材料和内部电极的非易失性存储器件公开(公告)号：US08698281B2
公开(公告)日：2014-04-15
申请号：US13655584
申请日：2012-10-19
发明人： In-Gyu Baek , Hyun-Jun Sim , Jin-Shi Zhao , Eun-Kyung Yim
IPC分类号： H01L29/00
CPC分类号： G11C13/0007 , G11C13/00 , G11C13/0004 , G11C13/0011 , G11C13/003 , G11C2213/31 , G11C2213/32 , G11C2213/78 , G11C2213/79 , H01L27/2436 , H01L27/249 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1226 , H01L45/146 , H01L45/1633
摘要： A nonvolatile memory device, a method of fabricating the nonvolatile memory device and a processing system including the nonvolatile memory device. The nonvolatile memory device may include a plurality of internal electrodes that extend in a direction substantially perpendicular to a face of a substrate, a plurality of first external electrodes that extend substantially in parallel with the face of the substrate, and a plurality of second external electrodes that also extend substantially in parallel with the face of the substrate. Each first external electrode is on a first side of a respective one of the internal electrodes, and each second external electrode is on a second side of a respective one of the internal electrodes. These devices also include a plurality of variable resistors that contact the internal electrodes, the first external electrodes and the second external electrodes.
摘要翻译： 非易失性存储器件，非易失性存储器件的制造方法和包括非易失性存储器件的处理系统。 非易失性存储装置可以包括沿基板垂直于基板的方向延伸的多个内部电极，基本上平行于基板的表面延伸的多个第一外部电极和多个第二外部电极 其也基本上平行于衬底的表面延伸。 每个第一外部电极在相应的一个内部电极的第一侧上，并且每个第二外部电极在相应的一个内部电极的第二侧上。 这些器件还包括接触内部电极，第一外部电极和第二外部电极的多个可变电阻器。
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3.发明申请Nonvolatile Memory Devices that Use Resistance Materials and Internal Electrodes 有权使用电阻材料和内部电极的非易失性存储器件公开(公告)号：US20130043453A1
公开(公告)日：2013-02-21
申请号：US13655584
申请日：2012-10-19
发明人： In-Gyu Baek , Hyun-Jun Sim , Jin-Shi Zhao , Eun-Kyung Yim
IPC分类号： H01L45/00
CPC分类号： G11C13/0007 , G11C13/00 , G11C13/0004 , G11C13/0011 , G11C13/003 , G11C2213/31 , G11C2213/32 , G11C2213/78 , G11C2213/79 , H01L27/2436 , H01L27/249 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1226 , H01L45/146 , H01L45/1633
摘要： A nonvolatile memory device, a method of fabricating the nonvolatile memory device and a processing system including the nonvolatile memory device. The nonvolatile memory device may include a plurality of internal electrodes that extend in a direction substantially perpendicular to a face of a substrate, a plurality of first external electrodes that extend substantially in parallel with the face of the substrate, and a plurality of second external electrodes that also extend substantially in parallel with the face of the substrate. Each first external electrode is on a first side of a respective one of the internal electrodes, and each second external electrode is on a second side of a respective one of the internal electrodes. These devices also include a plurality of variable resistors that contact the internal electrodes, the first external electrodes and the second external electrodes.
摘要翻译： 非易失性存储器件，非易失性存储器件的制造方法和包括非易失性存储器件的处理系统。 非易失性存储装置可以包括沿基板垂直于基板的方向延伸的多个内部电极，基本上平行于基板的表面延伸的多个第一外部电极和多个第二外部电极 其也基本上平行于衬底的表面延伸。 每个第一外部电极在相应的一个内部电极的第一侧上，并且每个第二外部电极在相应的一个内部电极的第二侧上。 这些器件还包括接触内部电极，第一外部电极和第二外部电极的多个可变电阻器。
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公开(公告)号：US09184218B2
公开(公告)日：2015-11-10
申请号：US14506005
申请日：2014-10-03
发明人： Lijie Zhang , Young-Bae Kim , Youn-Seon Kang , In-Gyu Baek , Masayuki Terai
CPC分类号： H01L27/249 , H01L27/2454 , H01L45/04 , H01L45/1226 , H01L45/146
摘要： A semiconductor memory device includes pillars extending upright on a substrate in a direction perpendicular to the substrate, a stack disposed on the substrate and constituted by a first interlayer insulating layer, a first conductive layer, a second interlayer insulating layer, and a second conductive layer, a variable resistance layer interposed between the pillars and the first conductive layer, and an insulating layer interposed between the first pillars and the second conductive layer.
摘要翻译： 半导体存储器件包括在垂直于衬底的方向上在衬底上直立延伸的柱，设置在衬底上并由第一层间绝缘层，第一导电层，第二层间绝缘层和第二导电层 插入在所述柱和所述第一导电层之间的可变电阻层以及插在所述第一柱和所述第二导电层之间的绝缘层。
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公开(公告)号：US09159914B2
公开(公告)日：2015-10-13
申请号：US14136522
申请日：2013-12-20
发明人： Eun-Kyung Yim , In-Gyu Baek , Jang-Eun Lee , Se-Chung Oh , Kyung-Tae Nam , Jin-Shi Zhao
IPC分类号： H01L27/108 , H01L27/112 , H01L45/00 , H01L27/24
CPC分类号： H01L45/1253 , H01L27/2409 , H01L27/2436 , H01L27/2463 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/145 , H01L45/146
摘要： A nonvolatile memory device includes a bottom electrode on a semiconductor substrate, a data storage layer on the bottom electrode, the data storage layer including a transition metal oxide, and a switching layer provided on a top surface and/or a bottom surface of the data storage layer, wherein a bond energy of material included in the switching layer and oxygen is more than a bond energy of a transition metal in the transition metal oxide and oxygen.
摘要翻译： 非易失性存储器件包括半导体衬底上的底电极，底电极上的数据存储层，包含过渡金属氧化物的数据存储层以及设置在数据的顶表面和/或底表面上的开关层 存储层，其中包含在所述开关层中的材料的键能和氧比所述过渡金属氧化物和氧中的过渡金属的键能大。
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公开(公告)号：US09118009B2
公开(公告)日：2015-08-25
申请号：US14318767
申请日：2014-06-30
发明人： Masayuki Terai , In-Gyu Baek
CPC分类号： H01L45/16 , H01L27/2409 , H01L45/04 , H01L45/1253 , H01L45/1266 , H01L45/146 , H01L45/1675
摘要： A method of fabricating a memory device includes defining a cell region on a substrate and defining a dummy region around the cell region, forming bit lines on a top surface of the substrate, the bit lines extending in one direction, forming cell vertical structures on top surfaces of the bit lines corresponding to the cell region, each cell vertical structure including a cell diode and a variable resistive element, forming dummy vertical structures on top surfaces of the bit lines corresponding to the dummy region, each dummy vertical structure including a dummy diode and a variable resistive element, and forming word lines in contact with top surfaces of the cell vertical structures and dummy vertical structures, the word lines intersecting the bit lines at right angles. The cell diode includes a first impurity pattern and a second impurity pattern, the dummy diode includes a first lightly doped impurity pattern and a second impurity pattern, and the variable resistive element includes a first electrode, a variable resistor, and a second electrode.
摘要翻译： 一种制造存储器件的方法包括限定衬底上的单元区域并且在单元区域周围限定虚拟区域，在衬底的顶表面上形成位线，沿着一个方向延伸的位线，在顶部形成单元垂直结构 对应于单元区域的位线的表面，每个单元垂直结构包括单元二极管和可变电阻元件，在与虚拟区对应的位线的顶表面上形成虚拟垂直结构，每个虚拟垂直结构包括虚拟二极管 和可变电阻元件，并且形成与单元垂直结构和虚拟垂直结构的顶表面接触的字线，字线与位线成直角相交。 电池二极管包括第一杂质图案和第二杂质图案，所述虚拟二极管包括第一轻掺杂杂质图案和第二杂质图案，并且所述可变电阻元件包括第一电极，可变电阻器和第二电极。
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公开(公告)号：US20150194603A1
公开(公告)日：2015-07-09
申请号：US14449425
申请日：2014-08-01
发明人： Masayuki Terai , In-Gyu Baek
CPC分类号： H01L27/2481 , H01L27/2409 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1675
摘要： Provided is a method of fabricating a memory device. The method includes defining a cell region and a driving region on a substrate, forming driving transistors on the driving region, forming a first bit line in the cell region, a first unit memory cell disposed on an upper surface of the first bit line, a word line disposed on upper surfaces of the first unit memory cells, and a second unit memory cell disposed on an upper surface of the word line, forming a planarization layer configured to fill between the second unit memory cells, and including second bit line grooves on the upper surfaces of the first bit lines, bit line contact vias in the second bit line grooves, floating electrode grooves on upper surfaces of ends of the word lines, and a first floating contact via and a second floating contact via in each of the floating electrode grooves, simultaneously forming second bit lines in the second bit line grooves, bit line contact electrodes in the bit line contact vias, floating electrodes in the floating electrode grooves, first floating contact electrodes in the first floating contact vias, and second floating contact electrodes in the second floating contact vias.
摘要翻译： 提供一种制造存储器件的方法。 该方法包括在衬底上限定单元区域和驱动区域，在驱动区域上形成驱动晶体管，在单元区域中形成第一位线，设置在第一位线的上表面上的第一单元存储单元， 设置在第一单元存储单元的上表面上的字线，以及设置在字线上表面上的第二单元存储单元，形成用于填充第二单元存储单元之间并包括第二位线槽的平坦化层 第一位线的上表面，第二位线槽中的位线接触通孔，字线的端部的上表面上的浮动电极沟槽以及浮动接触通路中的每一个中的第一浮动接触通孔和第二浮动接触通孔 电极沟槽，同时在第二位线沟槽中形成第二位线，位线接触通孔中的位线接触电极，浮动电极沟槽中的浮动电极，第一f 在第一浮动接触通孔中放置接触电极，以及在第二浮动接触通孔中的第二浮动接触电极。
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公开(公告)号：US09172039B2
公开(公告)日：2015-10-27
申请号：US14449425
申请日：2014-08-01
发明人： Masayuki Terai , In-Gyu Baek
IPC分类号： H01L21/336 , H01L45/00 , H01L27/24
CPC分类号： H01L27/2481 , H01L27/2409 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1675
摘要： Provided is a method of fabricating a memory device. The method includes defining a cell region and a driving region on a substrate, forming driving transistors on the driving region, forming a first bit line in the cell region, a first unit memory cell disposed on an upper surface of the first bit line, a word line disposed on upper surfaces of the first unit memory cells, and a second unit memory cell disposed on an upper surface of the word line, forming a planarization layer configured to fill between the second unit memory cells, and including second bit line grooves on the upper surfaces of the first bit lines, bit line contact vias in the second bit line grooves, floating electrode grooves on upper surfaces of ends of the word lines, and a first floating contact via and a second floating contact via in each of the floating electrode grooves, simultaneously forming second bit lines in the second bit line grooves, bit line contact electrodes in the bit line contact vias, floating electrodes in the floating electrode grooves, first floating contact electrodes in the first floating contact vias, and second floating contact electrodes in the second floating contact vias.
摘要翻译： 提供一种制造存储器件的方法。 该方法包括在衬底上限定单元区域和驱动区域，在驱动区域上形成驱动晶体管，在单元区域中形成第一位线，设置在第一位线的上表面上的第一单元存储单元， 设置在第一单元存储单元的上表面上的字线，以及设置在字线上表面上的第二单元存储单元，形成用于填充第二单元存储单元之间并包括第二位线槽的平坦化层 第一位线的上表面，第二位线槽中的位线接触通孔，字线的端部的上表面上的浮动电极沟槽以及浮动接触通路中的每一个中的第一浮动接触通孔和第二浮动接触通孔 电极沟槽，同时在第二位线沟槽中形成第二位线，位线接触通孔中的位线接触电极，浮动电极沟槽中的浮动电极，第一f 在第一浮动接触通孔中放置接触电极，以及在第二浮动接触通孔中的第二浮动接触电极。
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公开(公告)号：US20140124727A1
公开(公告)日：2014-05-08
申请号：US14136522
申请日：2013-12-20
发明人： Eun-Kyung Yim , In-Gyu Baek , Jang-Eun Lee , Se-Chung Oh , Kyung-Tae Nam , Jin-Shi Zhao
IPC分类号： H01L45/00
CPC分类号： H01L45/1253 , H01L27/2409 , H01L27/2436 , H01L27/2463 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/145 , H01L45/146
摘要： A nonvolatile memory device includes a bottom electrode on a semiconductor substrate, a data storage layer on the bottom electrode, the data storage layer including a transition metal oxide, and a switching layer provided on a top surface and/or a bottom surface of the data storage layer, wherein a bond energy of material included in the switching layer and oxygen is more than a bond energy of a transition metal in the transition metal oxide and oxygen.
摘要翻译： 非易失性存储器件包括半导体衬底上的底电极，底电极上的数据存储层，包含过渡金属氧化物的数据存储层以及设置在数据的顶表面和/或底表面上的开关层 存储层，其中包含在所述开关层中的材料的键能和氧比所述过渡金属氧化物和氧中的过渡金属的键能大。
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公开(公告)号：US20150104921A1
公开(公告)日：2015-04-16
申请号：US14318767
申请日：2014-06-30
发明人： Masayuki Terai , In-Gyu Baek
IPC分类号： H01L45/00
CPC分类号： H01L45/16 , H01L27/2409 , H01L45/04 , H01L45/1253 , H01L45/1266 , H01L45/146 , H01L45/1675
摘要： A method of fabricating a memory device includes defining a cell region on a substrate and defining a dummy region around the cell region, forming bit lines on a top surface of the substrate, the bit lines extending in one direction, forming cell vertical structures on top surfaces of the bit lines corresponding to the cell region, each cell vertical structure including a cell diode and a variable resistive element, forming dummy vertical structures on top surfaces of the bit lines corresponding to the dummy region, each dummy vertical structure including a dummy diode and a variable resistive element, and forming word lines in contact with top surfaces of the cell vertical structures and dummy vertical structures, the word lines intersecting the bit lines at right angles. The cell diode includes a first impurity pattern and a second impurity pattern, the dummy diode includes a first lightly doped impurity pattern and a second impurity pattern, and the variable resistive element includes a first electrode, a variable resistor, and a second electrode.
摘要翻译： 一种制造存储器件的方法包括限定衬底上的单元区域并且在单元区域周围限定虚拟区域，在衬底的顶表面上形成位线，沿着一个方向延伸的位线，在顶部形成单元垂直结构 对应于单元区域的位线的表面，每个单元垂直结构包括单元二极管和可变电阻元件，在与虚拟区对应的位线的顶表面上形成虚拟垂直结构，每个虚拟垂直结构包括虚拟二极管 和可变电阻元件，并且形成与单元垂直结构和虚拟垂直结构的顶表面接触的字线，字线与位线成直角相交。 电池二极管包括第一杂质图案和第二杂质图案，所述虚拟二极管包括第一轻掺杂杂质图案和第二杂质图案，并且所述可变电阻元件包括第一电极，可变电阻器和第二电极。
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