公开(公告)号：US10068767B2

公开(公告)日：2018-09-04

申请号：US15291377

申请日：2016-10-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Sik Seo ,  Seung-Heon Lee ,  Hyun-Woo Lee

IPC: H01L21/302 ,  H01L21/033 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/308

Abstract: A method for fabricating a semiconductor device includes forming a first mask pattern on a first film to extend in a first direction, forming a first spacer on either side wall of the first mask pattern, forming a second film to cover the first spacer and the first film, and forming a second mask pattern on the second film. The second mask pattern extends in a second direction different from the first direction. The method further includes forming a second spacer on either side wall of the second mask pattern, etching the first film using the first spacer and the second spacer as etch masks to form a contact pattern, and removing the first and second spacers to expose the contact pattern.

公开(公告)号：US20180006034A1

公开(公告)日：2018-01-04

申请号：US15698978

申请日：2017-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyong-Taek Lee ,  Sang-Woo Pae ,  Hye-Jin Kim ,  June-Kyun Park ,  Hyun-Woo Lee

IPC: H01L27/092 ,  H01L27/088 ,  H01L21/8234 ,  H01L27/11

CPC classification number: H01L27/0922 ,  G06F17/5022 ,  G06F17/5045 ,  G06F17/505 ,  G06F17/5081 ,  H01L21/823462 ,  H01L27/088 ,  H01L27/1104

Abstract: A system and method may determine the operating parameters, such as voltages, of MOS transistors within a circuit design by testing or simulation, for example and may identify a MOS transistor operating with its drain voltage higher than its gate voltage in the circuit. The design system and method may substitute a smaller transistor, having a high-k dielectric layer, for the original transistor in the circuit design.

公开(公告)号：US20160035607A1

公开(公告)日：2016-02-04

申请号：US14602584

申请日：2015-01-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Woo Lee ,  Chang-Woo Son ,  Yong-Jun Ahn ,  Tai-Jo Jeon

IPC: H01L21/677

CPC classification number: H01L21/6773 ,  H01L21/67294 ,  H01L21/67373 ,  H01L21/67379 ,  H01L21/67733 ,  H01L21/67736 ,  H01L21/67769 ,  H01L21/67772 ,  H01L21/67775

Abstract: A semiconductor wafer stocker apparatus includes a body frame, an inlet port to load a wafer shipping box into the body frame, an outlet port to unload the wafer shipping box from the body frame, an automated transfer robot operable to convey the wafer shipping box between the inlet port and the outlet port, and a shelf module within the body frame. The shelf module includes a shelf plate configured to support the wafer shipping box. The shelf plate includes first, second, and third protruding support pins arranged to align with respective grooves in an underside of the wafer shipping box and orient the wafer shipping box with a door thereof facing away from the body frame. The first and second support pins may be closer to the body frame than the third support pin. Related apparatus and methods of operation are also discussed.

Abstract translation: 半导体晶片储片器装置包括：主体框架，用于将晶片装运箱装载到主体框架中的入口端口，用于将晶片装运箱从主体框架卸载的出口;可操作以将晶片装运箱传送到 入口和出口，以及车体框架内的货架模块。 搁板模块包括构架成支撑晶片运输箱的搁板。 搁板包括第一，第二和第三突出支撑销，布置成与晶片运输箱的下侧中的相应凹槽对准，并且使晶片装运箱的门远离主体框架定向。 第一和第二支撑销可以比第三支撑销更靠近主体框架。 还讨论了相关装置和操作方法。

公开(公告)号：US09543178B2

公开(公告)日：2017-01-10

申请号：US14602584

申请日：2015-01-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Woo Lee ,  Chang-Woo Son ,  Yong-Jun Ahn ,  Tai-Jo Jeon

IPC: H01L21/677 ,  H01L21/67 ,  H01L21/673

CPC classification number: H01L21/6773 ,  H01L21/67294 ,  H01L21/67373 ,  H01L21/67379 ,  H01L21/67733 ,  H01L21/67736 ,  H01L21/67769 ,  H01L21/67772 ,  H01L21/67775

Abstract: A semiconductor wafer stocker apparatus includes a body frame, an inlet port to load a wafer shipping box into the body frame, an outlet port to unload the wafer shipping box from the body frame, an automated transfer robot operable to convey the wafer shipping box between the inlet port and the outlet port, and a shelf module within the body frame. The shelf module includes a shelf plate configured to support the wafer shipping box. The shelf plate includes first, second, and third protruding support pins arranged to align with respective grooves in an underside of the wafer shipping box and orient the wafer shipping box with a door thereof facing away from the body frame. The first and second support pins may be closer to the body frame than the third support pin. Related apparatus and methods of operation are also discussed.

Abstract translation: 半导体晶片储片器装置包括：主体框架，用于将晶片装运箱装载到主体框架中的入口端口，用于将晶片装运箱从主体框架卸载的出口;可操作以将晶片装运箱传送到 入口和出口，以及车体框架内的货架模块。 搁板模块包括构架成支撑晶片运输箱的搁板。 搁板包括第一，第二和第三突出支撑销，布置成与晶片运输箱的下侧中的相应凹槽对准，并且使晶片装运箱的门远离主体框架定向。 第一和第二支撑销可以比第三支撑销更靠近主体框架。 还讨论了相关装置和操作方法。

公开(公告)号：US10276571B2

公开(公告)日：2019-04-30

申请号：US15698978

申请日：2017-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyong-Taek Lee ,  Sang-Woo Pae ,  Hye-Jin Kim ,  June-Kyun Park ,  Hyun-Woo Lee

IPC: G06F17/50 ,  H01L27/092 ,  H01L27/088 ,  H01L27/00 ,  H01L27/11 ,  H01L21/8234

Abstract: A system and method may determine the operating parameters, such as voltages, of MOS transistors within a circuit design by testing or simulation, for example and may identify a MOS transistor operating with its drain voltage higher than its gate voltage in the circuit. The design system and method may substitute a smaller transistor, having a high-k dielectric layer, for the original transistor in the circuit design.