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    Nonvolatile memory system that erases memory cells when changing their mode of operation
    4.
    发明授权
    Nonvolatile memory system that erases memory cells when changing their mode of operation 有权

    公开(公告)号：US10115466B2

    公开(公告)日：2018-10-30

    申请号：US15687564

    申请日：2017-08-28

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyun-Wook Park ,  Kitae Park ,  Jaeyong Jeong

    IPC: G11C11/06 ,  G11C16/14 ,  G11C16/04 ,  G11C16/34 ,  G11C11/56 ,  G11C16/08 ,  G11C16/26

    Abstract: An method of operating a memory system including a plurality of memory cells includes changing an operation mode at least some of the memory cells which operate based on a first operation mode to operate based on a second operation mode; and performing a change erase operation on the memory cells for which an operation mode is changed on the basis of a change erase condition when the operation mode is changed. When memory cells operate in the first operation mode, a normal erase operation is performed based on a first erase condition, and when memory cells operate in the second operation mode, a normal erase operation is performed based on a second erase condition. The change erase condition is different from at least one of the first and second erase conditions.

    Signal adaptive filtering method, signal adaptive filter and computer readable medium for storing program therefor
    6.
    发明授权
    Signal adaptive filtering method, signal adaptive filter and computer readable medium for storing program therefor 有权
    信号自适应滤波方法，信号自适应滤波器和用于存储程序的计算机可读介质

    公开(公告)号：US08873643B2

    公开(公告)日：2014-10-28

    申请号：US14298530

    申请日：2014-06-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yung-Iyul Lee ,  Hyun-Wook Park

    IPC: H04N19/00 ,  H04N19/124 ,  H04N19/80 ,  H04N19/182 ,  H04N19/136

    CPC classification number: H04N19/00 ,  G06T5/00 ,  G06T5/002 ,  G06T5/20 ,  G06T2207/20008 ,  H04N19/117 ,  H04N19/124 ,  H04N19/127 ,  H04N19/136 ,  H04N19/14 ,  H04N19/157 ,  H04N19/159 ,  H04N19/172 ,  H04N19/182 ,  H04N19/189 ,  H04N19/44 ,  H04N19/48 ,  H04N19/527 ,  H04N19/60 ,  H04N19/61 ,  H04N19/80 ,  H04N19/86 ,  H04N19/90

    Abstract: A signal adaptive filtering method for reducing blocking effect and ringing noise, a signal adaptive filter, and a computer readable medium. The signal adaptive filtering method capable of reducing blocking effect and ringing noise of image data when a frame is composed of blocks of a predetermined size includes the steps of: (a) generating blocking information for reducing the blocking effect and ringing information for reducing the ringing noise, from coefficients of predetermined pixels of the upper and left boundary regions of the data block when a frame obtained by deconstructing a bitstream image data for inverse quantization is an intraframe; and (b) adaptively filtering the image data passed through inverse quantization and inverse discrete cosine transform according to the generated blocking information and ringing information. Therefore, the blocking effect and ringing noise can be eliminated from the image restored from the block-based image, thereby enhancing the image restored from compression.

    Abstract translation: 一种用于减少阻塞效应和振铃噪声的信号自适应滤波方法，信号自适应滤波器和计算机可读介质。 当帧由预定尺寸的块组成时，能够减少图像数据的阻塞效应和振铃噪声的信号自适应滤波方法包括以下步骤：（a）产生阻塞信息以减少阻塞效应和振铃信息以减少振铃 当通过解构用于逆量化的比特流图像数据而获得的帧是帧内时，来自数据块的上边界区域和左边界区域的预定像素的系数的噪声; 和（b）根据生成的阻塞信息和振铃信息自适应地过滤通过逆量化和逆离散余弦变换的图像数据。 因此，可以从基于块的图像恢复的图像中消除阻挡效果和振铃噪声，从而增强从压缩恢复的图像。

    Nonvolatile memory device with capability of determing degradation of data erase characteristics
    8.
    发明授权
    Nonvolatile memory device with capability of determing degradation of data erase characteristics 有权

    公开(公告)号：US11289170B2

    公开(公告)日：2022-03-29

    申请号：US17021407

    申请日：2020-09-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seong-Jin Song ,  Hyun-Wook Park ,  Bong-Soon Lim ,  Do-Bin Kim

    IPC: G11C16/34 ,  G11C16/04 ,  G11C16/14 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

    Abstract: A nonvolatile memory device includes a memory cell region and a peripheral circuit region. The memory cell region includes a memory block, and the peripheral circuit region includes a control circuit. The memory cell region includes a first metal pad. The peripheral circuit region includes a second metal pad and is vertically connected to the memory cell region by the first metal pad and the second metal pad. The memory block includes a plurality of memory cells disposed in a vertical direction. The control circuit determines whether a data erase characteristic for the memory block is degraded for each predetermined cycle of data erase operation, and performs a data erase operation by changing a level of a voltage applied to selection transistors for selecting the memory block as an erase target block when it is determined that the data erase characteristic is degraded.

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