公开(公告)号：US20240113163A1

公开(公告)日：2024-04-04

申请号：US18130732

申请日：2023-04-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： GEUNWOO KIM ,  WANDON KIM ,  HYUNWOO KANG ,  HYUNBAE LEE ,  JEONGHYUK YIM

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L27/092 ,  H01L29/42392 ,  H01L29/6656 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes; a substrate including an active pattern, a channel pattern and a source/drain pattern on the active pattern, wherein the channel pattern is connected to the source/drain pattern, a gate electrode on the channel pattern, and a gate contact connected to a top surface of the gate electrode, wherein the gate contact includes a capping layer directly contacting the top surface of the gate electrode and a metal layer on the capping layer, wherein the capping layer and the metal layer include the same metal, a concentration of oxygen in the metal layer ranges from between about 2 at % to about 10 at %, and a maximum concentration of oxygen in the capping layer ranges from between about 15 at % to about 30 at %.

公开(公告)号：US20200013898A1

公开(公告)日：2020-01-09

申请号：US16458412

申请日：2019-07-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JEONGHYUK YIM ,  WANDON KIM ,  WEONHONG KIM ,  JONGHO PARK ,  HYEONJUN BAEK ,  BYOUNGHOON LEE ,  SANGJIN HYUN

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/51 ,  H01L21/28 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/08

Abstract: A semiconductor device includes a substrate including first and second active regions, first and second active patterns disposed on the first and second active regions, respectively, first and second gate electrodes crossing the first and second active patterns, respectively, a first gate insulating pattern interposed between the first active pattern and the first gate electrode, and a second gate insulating pattern interposed between the second active pattern and the second gate electrode. The first gate insulating pattern includes a first dielectric pattern and a first ferroelectric pattern disposed on the first dielectric pattern. The second gate insulating pattern includes a second dielectric pattern. A threshold voltage of a transistor in the first active region is different from a threshold voltage of a transistor in the second active region.

公开(公告)号：US20240170486A1

公开(公告)日：2024-05-23

申请号：US18425476

申请日：2024-01-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JEONGHYUK YIM ,  KI-IL KIM ,  GIL HWAN SON ,  KANG ILL SEO

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/0922 ,  H01L21/82385 ,  H01L21/823857 ,  H01L21/823871 ,  H01L29/0665 ,  H01L29/401 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78645

Abstract: Integrated circuit devices may include two transistor stacks including lower transistors having different threshold voltages and upper transistors having different threshold voltages. Gate insulators of the lower transistors may have different dipole elements or different areal densities of dipole elements, and the upper transistors may have different gate electrode structures.

公开(公告)号：US20230142609A1

公开(公告)日：2023-05-11

申请号：US17574043

申请日：2022-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： JEONGHYUK YIM ,  KANG-ILL SEO

IPC: H01L29/423 ,  H01L29/167 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L29/42392 ,  H01L29/167 ,  H01L27/0928 ,  H01L21/823857

Abstract: Integrated circuit devices may include a stacked structure including an upper transistor on a substrate and a lower transistor between the substrate and the upper transistor. The upper transistor may include an upper gate electrode, an upper active region in the upper gate electrode, and an upper gate insulator between the upper gate electrode and the upper active region. The upper active region may include an inner layer including a first semiconductor material and an outer layer that extends between the inner layer and the upper gate insulator and includes a second semiconductor material that is different from the first semiconductor material. The lower transistor may include a lower gate electrode, a lower active region in the lower gate electrode, and a lower gate insulator between the lower gate electrode and the lower active region.

公开(公告)号：US20220375935A1

公开(公告)日：2022-11-24

申请号：US17387178

申请日：2021-07-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： JEONGHYUK YIM ,  KI-IL KIM ,  GIL HWAN SON ,  KANG ILL SEO

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/40 ,  H01L29/66 ,  H01L29/786 ,  H01L21/8238

Abstract: Integrated circuit devices may include two transistor stacks including lower transistors having different threshold voltages and upper transistors having different threshold voltages. Gate insulators of the lower transistors may have different dipole elements or different areal densities of dipole elements, and the upper transistors may have different gate electrode structures.

公开(公告)号：US20210005729A1

公开(公告)日：2021-01-07

申请号：US17024813

申请日：2020-09-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： JONGHAN LEE ,  WANDON KIM ,  JAEYEOL SONG ,  JEONGHYUK YIM ,  HYUNGSUK JUNG

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/51 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/768

Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a gate electrode on a substrate, an upper capping pattern on the gate electrode, and a lower capping pattern between the gate electrode and the upper capping pattern. The lower capping pattern comprises a first portion between the gate electrode and the upper capping pattern, and a plurality of second portions extending from the first portion onto corresponding side surfaces of the upper capping pattern. The upper capping pattern covers a topmost surface of each of the second portions.

公开(公告)号：US20190165114A1

公开(公告)日：2019-05-30

申请号：US15990983

申请日：2018-05-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： JONGHAN LEE ,  WANDON KIM ,  JAEYEOL SONG ,  JEONGHYUK YIM ,  HyungSuk JUNG

IPC: H01L29/423 ,  H01L21/28 ,  H01L29/51 ,  H01L27/088

Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a gate electrode on a substrate, an upper capping pattern on the gate electrode, and a lower capping pattern between the gate electrode and the upper capping pattern. The lower capping pattern comprises a first portion between the gate electrode and the upper capping pattern, and a plurality of second portions extending from the first portion onto corresponding side surfaces of the upper capping pattern. The upper capping pattern covers a topmost surface of each of the second portions.