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    NON-VOLATILE MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME AND PROGRAM METHOD THEREOF
    3.
    发明申请
    NON-VOLATILE MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME AND PROGRAM METHOD THEREOF 有权

    公开(公告)号：US20220068397A1

    公开(公告)日：2022-03-03

    申请号：US17523385

    申请日：2021-11-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： WON-TAECK JUNG ,  SANG-WAN NAM ,  JINWOO PARK ,  JAEYONG JEONG

    IPC: G11C16/20 ,  G11C16/08 ,  G11C16/34 ,  G11C16/04 ,  G11C16/10

    Abstract: A three-dimensional (3D) nonvolatile memory device includes a cell string. The cell string includes a pillar structure comprising a ground selection transistor, a plurality of memory cells, and a string selection transistor stacked vertically over a substrate. The memory cells comprise a first cell group and a second cell group stacked on the first cell group, and a horizontal width of at least a portion of the pillar structure decreases in a depth direction towards the substrate. A method of programming the memory device includes initializing a channel of a memory cell of the first cell group of the cell string through the ground selection transistor of the pillar structure, and then applying a program voltage to the memory cell of the pillar structure of the cell string.

    SEMICONDUCTOR PACKAGE
    6.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20230113726A1

    公开(公告)日：2023-04-13

    申请号：US17872139

    申请日：2022-07-25

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： BYOUNGSOO KWAK ,  JINWOO PARK

    IPC: H01L23/31 ,  H01L25/065 ,  H01L23/13

    Abstract: A semiconductor package includes an interposer; a first stacked chip including a first semiconductor chip disposed on the interposer and one or more second semiconductor chips disposed on the first semiconductor chip; a first molding layer surrounding the first stacked chip; and a second molding layer surrounding the first molding layer, wherein the second molding layer extends from an uppermost surface of the interposer to a trench of the interposer.

    SEMICONDUCTOR PACKAGE INCLUDING MOLD LAYER AND MANUFACTURING METHOD THEREOF
    7.
    发明申请
    SEMICONDUCTOR PACKAGE INCLUDING MOLD LAYER AND MANUFACTURING METHOD THEREOF 有权

    公开(公告)号：US20220293563A1

    公开(公告)日：2022-09-15

    申请号：US17405130

    申请日：2021-08-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： YEONGKWON KO ,  JINWOO PARK ,  JAEKYUNG YOO ,  TEAKHOON LEE

    IPC: H01L25/065 ,  H01L21/56 ,  H01L25/00 ,  H01L23/00

    Abstract: A semiconductor package includes a package substrate on which a base chip is disposed. A first semiconductor chip is disposed on the base chip. A second semiconductor chip is disposed on the first semiconductor chip. An inner mold layer surrounds an upper surface of the base chip and respective side surfaces of the first semiconductor chip and the second semiconductor chip. A first outer mold layer is interposed between the package substrate and the base chip while covering at least a portion of a side surface of the base chip. A second outer mold layer is disposed on the first outer mold layer while covering at least a portion of a side surface of the inner mold layer. The second outer mold layer is spaced apart from the package substrate. The first outer mold layer and the second outer mold layer have different viscosities.

    SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURE
    8.
    发明申请
    SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURE 有权

    公开(公告)号：US20220093481A1

    公开(公告)日：2022-03-24

    申请号：US17177725

    申请日：2021-02-17

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： JINWOO PARK ,  JONGHO LEE ,  YEONGKWON KO

    IPC: H01L23/31 ,  H01L25/18 ,  H01L23/29 ,  H01L23/498 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56

    Abstract: A method of manufacture for a semiconductor package includes; forming a molding member on side surfaces of the semiconductor chips, using an adhesive to attach a carrier substrate to upper surfaces of the molding member and the semiconductor chips, using a first blade having a first blade-width to cut away selected portions of the carrier substrate and portions of the adhesive underlying the selected portions of the carrier substrate, and using the first blade to partially cut into an upper surface of the molding member to form a first cutting groove, wherein the selected portions of the carrier substrate are dispose above portions of the molding member between adjacent ones of semiconductor chips, using a second blade having a second blade-width narrower than the first blade-width to cut through a lower surface of the molding member to form a second cutting groove, wherein a combination of the first cutting groove and the second cutting groove separate a package structure including a semiconductor chip supported by a cut portion of the carrier substrate and bonding the package structure to an upper surface of a package substrate.

    SEMICONDUCTOR DEVICES AND ELECTRONIC SYSTEMS INCLUDING THE SAME
    9.
    发明申请
    SEMICONDUCTOR DEVICES AND ELECTRONIC SYSTEMS INCLUDING THE SAME 有权

    公开(公告)号：US20220139456A1

    公开(公告)日：2022-05-05

    申请号：US17353918

    申请日：2021-06-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： GEUNWON LIM ,  JINWOO PARK ,  ILGYU CHOI

    IPC: G11C16/04 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

    Abstract: Semiconductor devices may include a peripheral circuit structure including circuits, a substrate on the peripheral circuit structure, a pair of word line cut structures extending in a first direction on the substrate, and a memory cell block between the pair of word line cut structures and on the substrate. The memory cell block may include a memory stack structure including gate lines overlapping each other in a vertical direction, an interlayer insulation layer on an edge portion of each of the gate lines, a dam structure extending through the gate lines and the interlayer insulation layer, an intersection direction cut structure extending through the memory stack structure and the interlayer insulation layer in the vertical direction and being spaced apart from the dam structure, and a dummy channel structures between the intersection direction cut structure and the dam structure.

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