公开(公告)号：US10700193B2

公开(公告)日：2020-06-30

申请号：US16414186

申请日：2019-05-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-hyun Yoo ,  Ui-hui Kwon ,  Da-won Jeong ,  Jae-ho Kim ,  Jun-hyeok Kim ,  Kang-hyun Baek ,  Kyu-ok Lee

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L29/40 ,  H01L29/06

Abstract: A power device includes a drift layer of a second conductivity type located on a semiconductor layer of a first conductivity type, a first source region of the second conductivity type and a second source region of the second conductivity type, located on the drift layer to be apart from each other, and a gate electrode on the drift layer between the first and second source regions with a gate insulating layer between the gate electrode and the drift layer, wherein the gate electrode includes a first gate electrode and a second gate electrode adjacent to the first source region and the second source region, respectively, and a third gate electrode between the first and second gate electrodes, wherein the third gate electrode is floated or grounded.

公开(公告)号：US20200144411A1

公开(公告)日：2020-05-07

申请号：US16414186

申请日：2019-05-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-hyun YOO ,  Ui-hui Kwon ,  Da-won Jeong ,  Jae-ho Kim ,  Jun-hyeok Kim ,  Kang-hyun Baek ,  Kyu-ok Lee

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423

Abstract: A power device includes a drift layer of a second conductivity type located on a semiconductor layer of a first conductivity type, a first source region of the second conductivity type and a second source region of the second conductivity type, located on the drift layer to be apart from each other, and a gate electrode on the drift layer between the first and second source regions with a gate insulating layer between the gate electrode and the drift layer, wherein the gate electrode includes a first gate electrode and a second gate electrode adjacent to the first source region and the second source region, respectively, and a third gate electrode between the first and second gate electrodes, wherein the third gate electrode is floated or grounded.

公开(公告)号：US09437452B2

公开(公告)日：2016-09-06

申请号：US14604123

申请日：2015-01-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeong-ju Park ,  Hyoung-hee Kim ,  Kyoung-mi Kim ,  Se-kyung Baek ,  Soo-jin Lee ,  Jae-ho Kim ,  Jung-sik Choi

IPC: H01L21/311 ,  H01L21/3105 ,  H01L21/027 ,  H01L21/033 ,  H01L21/308 ,  H01L21/3213 ,  G03F7/00

CPC classification number: H01L21/31144 ,  G03F7/0002 ,  H01L21/0273 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31058 ,  H01L21/32139

Abstract: A method of forming a fine pattern includes forming a phase separation guide layer on a substrate, forming a neutral layer on the phase separation guide layer, forming a first pattern including first openings on the neutral layer, forming a second pattern including second openings each having a smaller width than each of the first openings, forming a neutral pattern including guide patterns exposing a portion of the phase separation guide layer by etching an exposed portion of the neutral layer by using the second pattern as an etch mask, removing the second pattern to expose a top surface of the neutral pattern, forming a material layer including a block copolymer on the neutral pattern and the phase separation guide layer exposed through the guide patterns, and forming a fine pattern layer including a first block and a second block on the neutral pattern and the phase separation guide layer.

Abstract translation: 形成精细图案的方法包括在基板上形成相分离引导层，在相分离引导层上形成中性层，在中性层上形成包括第一开口的第一图案，形成包括第二开口的第二图案， 比每个第一开口更小的宽度，通过使用第二图案作为蚀刻掩模蚀刻中性层的暴露部分，形成包括暴露一部分相分离引导层的引导图案的中性图案，将第二图案去除 露出中性图案的顶面，在中性图案上形成包含嵌段共聚物的材料层，通过引导图案露出相分离引导层，并在中性线上形成包括第一块和第二块的精细图案层 图案和相分离引导层。