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公开(公告)号：US12062826B2
公开(公告)日：2024-08-13
申请号：US17515055
申请日：2021-10-29
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jaehyeong Lee , Hyeokshin Kwon , Jaeho Shin , Taehwan Jang , Insu Jeon
Abstract: A qubit memory of a quantum computer is provided. The qubit memory according to an embodiment includes a first readout unit, a first transmon, and a first data storage unit storing quantum information, and the first data storage unit includes a first superconducting waveguide layer, an insulating layer, and a superconductor layer sequentially stacked on a substrate. In one example, the first superconducting waveguide layer may include a superconducting resonator.
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公开(公告)号：US20240099161A1
公开(公告)日：2024-03-21
申请号：US18116681
申请日：2023-03-02
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jaehyeong Lee , Jinhyoun Kang , Jaeho Shin , Daeseok Han
CPC classification number: H10N60/805 , H10N60/0912 , H10N60/12
Abstract: A Josephson junction device and a method of manufacturing the Josephson junction device are disclosed. The Josephson junction device includes a substrate having a top surface and a trench recessed below the first surface, wherein sidewalls of the substrate define sidewalls of the trench; a first superconducting electrode formed on the top surface of the substrate with sidewalls further defining the sidewalls of the trench; a tunneling thin film formed over the sidewalls of the substrate and over the sidewalls of the first superconducting electrode; and a second superconducting electrode formed in the trench in contact with the tunneling thin film and with top surface above the top surface of the substrate, wherein a superconducting tunnel junction is formed between the first superconducting electrode and the second superconducting electrode through the tunneling thin film.
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公开(公告)号：US11586543B2
公开(公告)日：2023-02-21
申请号：US17380805
申请日：2021-07-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jeongho Lee , Heehyun Nam , Jaeho Shin , Hyodeok Shin , Younggeon Yoo , Younho Jeon , Wonseb Jeong , Ipoom Jeong , Hyeokjun Choe
IPC: G06F12/00 , G06F12/0817 , G06F3/06 , G06F12/0862
Abstract: A device connected to a host processor via a bus includes: an accelerator circuit configured to operate based on a message received from the host processor; and a controller configured to control an access to a memory connected to the device, wherein the controller is further configured to, in response to a read request received from the accelerator circuit, provide a first message requesting resolution of coherence to the host processor and prefetch first data from the memory.
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公开(公告)号：US20230185717A1
公开(公告)日：2023-06-15
申请号：US18166244
申请日：2023-02-08
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jeongho LEE , Heehyun Nam , Jaeho Shin , Hyodeok Shin , Younggeon Yoo , Younho Jeon , Wonseb Jeong , Ipoom Jeong , Hyeokjun Choe
IPC: G06F12/0817 , G06F3/06 , G06F12/0862
CPC classification number: G06F12/0828 , G06F3/0622 , G06F3/0655 , G06F3/0679 , G06F12/0862 , G06F2212/602 , G06F2212/621
Abstract: A device connected to a host processor via a bus includes: an accelerator circuit configured to operate based on a message received from the host processor; and a controller configured to control an access to a memory connected to the device, wherein the controller is further configured to, in response to a read request received from the accelerator circuit, provide a first message requesting resolution of coherence to the host processor and prefetch first data from the memory.
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公开(公告)号：US20220271212A1
公开(公告)日：2022-08-25
申请号：US17555812
申请日：2021-12-20
Applicant: Samsung Electronics Co., Ltd.
Inventor： Taehwan Jang , Hyeokshin Kwon , Jaeho Shin , Jaehyeong Lee , Insu Jeon , Sungho Han
Abstract: A multi-mode resonator is provided. The multi-mode resonator includes a housing and a cavity disposed in the housing, wherein the cavity includes a main cavity and a plurality of first subcavities disposed on a first lateral side of the main cavity.
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Patent Agency Ranking
公开(公告)号：US20240363989A1
公开(公告)日：2024-10-31
申请号：US18770206
申请日：2024-07-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jaehyeong Lee , Hyeokshin Kwon , Jaeho Shin , Taehwan Jang , Insu Jeon
Abstract: A qubit memory of a quantum computer is provided. The qubit memory according to an embodiment includes a first readout unit, a first transmon, and a first data storage unit storing quantum information, and the first data storage unit includes a first superconducting waveguide layer, an insulating layer, and a superconductor layer sequentially stacked on a substrate. In one example, the first superconducting waveguide layer may include a superconducting resonator.
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公开(公告)号：US12007884B2
公开(公告)日：2024-06-11
申请号：US17895260
申请日：2022-08-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jaeho Shin , Jeongho Lee , Younggeon Yoo , Hyeokjun Choe
CPC classification number: G06F12/02 , G06F12/14 , H04L9/0825
Abstract: In a method of allocating and protecting a memory in a computational storage device including a first computing engine and a buffer memory, a memory allocation request is received from a host device that is disposed outside the computational storage device. Based on the memory allocation request, a memory allocation operation in which a first memory region is generated in the buffer memory and a first key associated with the first memory region is generated is performed. A program execution request is received from the host device. Based on the program execution request, a program execution operation is performed in which a first program is executed by the first computing engine by accessing the first memory region based on an encryption or a decryption using the first key.
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公开(公告)号：US11983115B2
公开(公告)日：2024-05-14
申请号：US18166244
申请日：2023-02-08
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jeongho Lee , Heehyun Nam , Jaeho Shin , Hyodeok Shin , Younggeon Yoo , Younho Jeon , Wonseb Jeong , Ipoom Jeong , Hyeokjun Choe
IPC: G06F12/0817 , G06F3/06 , G06F12/0862
CPC classification number: G06F12/0828 , G06F3/0622 , G06F3/0655 , G06F3/0679 , G06F12/0862 , G06F2212/602 , G06F2212/621
Abstract: A device connected to a host processor via a bus includes: an accelerator circuit configured to operate based on a message received from the host processor; and a controller configured to control an access to a memory connected to the device, wherein the controller is further configured to, in response to a read request received from the accelerator circuit, provide a first message requesting resolution of coherence to the host processor and prefetch first data from the memory.
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公开(公告)号：US11742046B2
公开(公告)日：2023-08-29
申请号：US17318234
申请日：2021-05-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jeongho Lee , Kwangjin Lee , Hee Hyun Nam , Jaeho Shin , Youngkwang Yoo
CPC classification number: G11C29/42 , G11C7/1012 , G11C7/1063 , G11C29/18 , G11C29/44
Abstract: Disclosed is a method of performing, at a controller, an access to a memory device, which includes transmitting, at the controller, a first command signal, a first address signal, and a first swizzling signal to the memory device, selecting first data bits stored in a memory cell array of the memory device based on the first command signal and the first address signal, and sequentially outputting, at the memory device, at least a part of the first data bits to the controller in a burst manner, based on the first swizzling signal.
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公开(公告)号：US20220121574A1
公开(公告)日：2022-04-21
申请号：US17380805
申请日：2021-07-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jeongho LEE , Heehyun Nam , Jaeho Shin , Hyodeok Shin , Younggeon Yoo , Younho Jeon , Wonseb Jeong , Ipoom Jeong , Hyeokjun Choe
IPC: G06F12/0817 , G06F3/06 , G06F12/0862
Abstract: A device connected to a host processor via a bus includes: an accelerator circuit configured to operate based on a message received from the host processor; and a controller configured to control an access to a memory connected to the device, wherein the controller is further configured to, in response to a read request received from the accelerator circuit, provide a first message requesting resolution of coherence to the host processor and prefetch first data from the memory.
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