公开(公告)号：US20240242770A1

公开(公告)日：2024-07-18

申请号：US18400049

申请日：2023-12-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hojoon KIM ,  Jae-Duk YU ,  Yohan LEE ,  Jiho CHO

IPC: G11C16/34 ,  G11C16/04

CPC classification number: G11C16/3427 ,  G11C16/0483

Abstract: A non-volatile memory device according to some example embodiments includes a memory block including a plurality of cell strings including a plurality of string selection transistors and a plurality of memory cells, a first string selection line connected to a string selection transistor of a first cell string of the plurality of cell strings, and a second string selection line connected to a string selection transistor of a second cell string of the plurality of cell strings; and a control circuit configured to control a recovery operation to apply a recovery voltage with different driving strengths to the first string selection line and the second string selection line.

公开(公告)号：US20230143210A1

公开(公告)日：2023-05-11

申请号：US17750315

申请日：2022-05-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanggi HONG ,  Chaehoon KIM ,  Sangwon PARK ,  Jiho CHO

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/24

Abstract: In a method of operating a nonvolatile memory device that includes a memory block including cell strings where each of the cell strings includes a string selection transistor, memory cells and a ground selection transistor which are connected in series and disposed in a vertical direction, each of word-lines coupled to the memory cells is set up to a respective target level during a word-line set-up period, a sensing operation on target memory cells is performed by applying a read voltage to a selected word-line coupled to the target memory cells while applying a read pass voltage to unselected word-lines during a sensing period, and while consuming an internal voltage connected to the unselected word-lines in a particular circuit in the nonvolatile memory device, a voltage level of the unselected word-lines is recovered to a level of the internal voltage during a discharge period of a word-line recovery period.

公开(公告)号：US20230134907A1

公开(公告)日：2023-05-04

申请号：US17750642

申请日：2022-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yohan LEE ,  Chaehoon KIM ,  Jungyun YUN ,  Jiho CHO ,  Sanggi HONG

IPC: G11C16/14 ,  G11C16/04 ,  G11C16/08 ,  G11C16/30

Abstract: A nonvolatile memory device includes a memory block and a control circuit. The memory block includes a plurality of cell strings where each of the plurality of cell strings includes a string selection transistor, a plurality of memory cells and a ground selection transistor which are connected in series and disposed in a vertical direction between a bit-line and a common source line. The control circuit adjusts a level of a high voltage applied to a gate of a pass transistor of a selected word-line such that a voltage difference between the high voltage and a program voltage applied to a drain of the pass transistor differs in at least a portion of a plurality of program loops based on a comparison of a number of the program loops and a reference number during a program operation on a target memory cells.

公开(公告)号：US20220122651A1

公开(公告)日：2022-04-21

申请号：US17322065

申请日：2021-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoonjee KIM ,  Seungyeon KIM ,  Sangwan NAM ,  Hongsoo JEON ,  Jiho CHO

IPC: G11C11/4097 ,  G11C11/408 ,  G11C11/4093 ,  G11C11/4099 ,  G11C5/06

Abstract: A memory device includes a peripheral circuit area including a first substrate and circuit elements on the first substrate, at least a portion of the circuit elements providing a source driver, and a cell area including a second substrate stacked with the peripheral circuit area in a first direction, perpendicular to an upper surface of the first substrate, and cell blocks and dummy blocks arranged in a second direction, parallel to an upper surface of the second substrate. Each of the cell blocks includes gate electrode layers and insulating layers alternately stacked on the second substrate, and channel structures extending in the first direction to penetrate through the gate electrode layers and the insulating layers and to be connected to the second substrate, at least one source contact block, among the dummy blocks, includes a first dummy insulating region on the second substrate, and source contacts extending in the first direction, penetrating through the first dummy insulating region and connected to the second substrate, and the source contacts are connected to the source driver through metal wirings in an upper portion of the cell area.