公开(公告)号：US09548401B2

公开(公告)日：2017-01-17

申请号：US14698909

申请日：2015-04-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Hyun Yoo ,  Jin-Hyun Noh ,  Su-Tae Kim ,  Byeong-Ryeol Lee ,  Seong-Hun Jang ,  Jong-Sung Jeon

IPC: H01L29/02 ,  H01L29/94 ,  H01L29/78 ,  H01L27/06 ,  H01L29/10

CPC classification number: H01L29/94 ,  H01L27/0629 ,  H01L29/1041 ,  H01L29/7833 ,  H01L29/7838 ,  H01L29/7851

Abstract: A semiconductor device includes a substrate including a first impurity diffusion region having a first doping concentration and at least one second impurity diffusion region having a second doping concentration different from the first doping concentration, the at least one second impurity region being surrounded by the first impurity diffusion region; at least one electrode facing the first impurity diffusion region and the at least one second impurity diffusion region; and at least one insulating layer between the first impurity diffusion region and the at least one electrode, and between the at least one second impurity diffusion region and the at least one electrode.

Abstract translation: 一种半导体器件包括：衬底，其包括具有第一掺杂浓度的第一杂质扩散区域和具有不同于第一掺杂浓度的第二掺杂浓度的至少一个第二杂质扩散区域，所述至少一个第二杂质区域被第一杂质包围 扩散区; 面向所述第一杂质扩散区域和所述至少一个第二杂质扩散区域的至少一个电极; 以及在所述第一杂质扩散区域和所述至少一个电极之间以及所述至少一个第二杂质扩散区域和所述至少一个电极之间的至少一个绝缘层。

公开(公告)号：US09935167B2

公开(公告)日：2018-04-03

申请号：US15268833

申请日：2016-09-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Hyun Noh ,  Su-Tae Kim ,  Jae-Hyun Yoo ,  Byeong-Ryeol Lee ,  Jong-Sung Jeon

IPC: H01L29/00 ,  H01L29/06 ,  H01L29/78 ,  H01L29/161 ,  H01L27/088 ,  H01L29/423 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L27/092 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/063 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/0619 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1054 ,  H01L29/1095 ,  H01L29/161 ,  H01L29/165 ,  H01L29/408 ,  H01L29/4238 ,  H01L29/66545 ,  H01L29/66659 ,  H01L29/7816 ,  H01L29/7835 ,  H01L29/785 ,  H01L29/7851

Abstract: Semiconductor devices include a channel layer on a substrate, the channel layer including a material having a lattice constant different from a lattice constant of the substrate, a first gate electrode on the channel layer, a first source region of a first conductivity type at a first side of the first gate electrode, a first body region of a second conductivity type under the first source region and contacting the first source region, a first drain region of the first conductivity type disposed at a second side of the first gate electrode, a first drift region of the first conductivity type under the first drain region and contacting the first drain region, and a first stud region in the channel layer and the first drift region. The first stud region has an impurity concentration higher than an impurity concentration of the first drift region.

公开(公告)号：US10084079B2

公开(公告)日：2018-09-25

申请号：US15052177

申请日：2016-02-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hyun Yoo ,  Kwan-Young Kim ,  Jin-Hyun Noh ,  Kee-Moon Chun ,  Yong-Woo Jeon

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7816 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/66795 ,  H01L29/7835 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor device includes a first well disposed in a substrate and including a first impurity of a first conductivity type, a second well disposed in the substrate, including a second impurity of a second conductivity type different from the first conductivity type, and having first to third portions, and a gate structure formed on the first well and the second well, wherein the second portion is disposed between the first portion and the third portion, the first portion and the third portion are formed deeper than the second portion, and concentration of the second impurity of the first portion and the third portion is greater than concentration of the second impurity of the second portion.

公开(公告)号：US10056479B2

公开(公告)日：2018-08-21

申请号：US14993108

申请日：2016-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Hyun Yoo ,  Jin-Hyun Noh ,  Kee-Moon Chun ,  Jong-Sung Jeon

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/165

CPC classification number: H01L29/7816 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/165 ,  H01L29/7835 ,  H01L29/7848 ,  H01L29/7851

Abstract: A semiconductor device has reduced ON resistance (Ron) as well as a reduced electric field emanating from a current path. The semiconductor device includes a fin pattern, a gate electrode intersecting the fin pattern, a source region which has a first conductivity type and is disposed on one side of the gate electrode, a body region which has a second conductivity type, is situated within the fin pattern under the source region, and extends in a loop around the source region, a drain region which has the first conductivity type and is disposed on the other side of the gate electrode, a field dispersion region which has the second conductivity type and is situated within the fin pattern between the gate electrode and the drain region, and a drift region which has the first conductivity type, is situated within the fin pattern under the drain region and the field dispersion region, and extends in a loop around the drain region and the field dispersion region.

公开(公告)号：US09941280B2

公开(公告)日：2018-04-10

申请号：US15228292

申请日：2016-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwan-Young Kim ,  Jae-Hyun Yoo ,  Jin-Hyun Noh ,  Woo-Yeol Maeng ,  Yong-Woo Jeon

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/08 ,  H01L23/528

CPC classification number: H01L27/0886 ,  H01L23/528 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0865 ,  H01L29/0873 ,  H01L29/0882 ,  H01L29/4232 ,  H01L29/4236 ,  H01L29/7816 ,  H01L29/7835 ,  H01L29/785

Abstract: According to example embodiments, a semiconductor device includes a first fin, a second fin that is separated from the first fin, and a gate on the first fin and the second fin. The gate crosses the first fin and the second fin. The first fin includes a first doped area at both sides of the gate. The first doped area is configured to have a first voltage applied thereto. The second fin includes a second doped area at both sides of the gate. The second doped area is configured to have a second voltage applied thereto. The second voltage is different than the first voltage.

公开(公告)号：US09576953B2

公开(公告)日：2017-02-21

申请号：US14488628

申请日：2014-09-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kang-Hyun Baek ,  Jin-Hyun Noh ,  Tae-Joong Song ,  Gi-Young Yang ,  Sang-Kyu Oh

IPC: H01L27/088 ,  H01L29/417 ,  H01L29/78 ,  H01L27/11 ,  G06F17/50

CPC classification number: H01L27/0886 ,  G06F17/5068 ,  H01L27/1104 ,  H01L29/785 ,  H01L29/7851

Abstract: A layout design system for designing a semiconductor device includes a processor, a storage module storing an intermediate design, and a correction module used by the processor to correct the intermediate design. The intermediate design includes an active region and dummy designs on the active region. Each dummy design includes a dummy structure and dummy spacers disposed at opposite sides of the dummy structure. The correction module is configured to alter widths of regions of at least some of the dummy designs. The corrected design is used to produce a semiconductor device having an active fin, a hard mask layer disposed on the active fin, a gate structure crossing the over the hard mask layer, and a spacer disposed on at least one side of the gate structure. The hard mask layer, and the active fin, are provided with widths that vary due to the dummy designs.

Abstract translation: 用于设计半导体器件的布局设计系统包括处理器，存储中间设计的存储模块和由处理器用于校正中间设计的校正模块。 中间设计包括有源区域和有源区域的虚拟设计。 每个虚拟设计包括虚拟结构和设置在虚拟结构的相对侧的虚设间隔物。 校正模块被配置为改变至少一些虚拟设计的区域的宽度。 校正后的设计用于制造具有活性鳍片，设置在活性鳍片上的硬掩模层，与硬掩模层之间交叉的栅极结构以及设置在栅极结构的至少一侧上的间隔物的半导体器件。 硬掩模层和活动翅片具有由于虚拟设计而变化的宽度。

公开(公告)号：US20160372593A1

公开(公告)日：2016-12-22

申请号：US15052177

申请日：2016-02-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hyun YOO ,  Kwan-Young Kim ,  Jin-Hyun Noh ,  Kee-Moon Chun ,  Yong-Woo Jeon

IPC: H01L29/78 ,  H01L21/324 ,  H01L21/265 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/66795 ,  H01L29/7835 ,  H01L29/7851

Abstract: A semiconductor device includes a first well disposed in a substrate and including a first impurity of a first conductivity type, a second well disposed in the substrate, including a second impurity of a second conductivity type different from the first conductivity type, and having first to third portions, and a gate structure formed on the first well and the second well, wherein the second portion is disposed between the first portion and the third portion, the first portion and the third portion are formed deeper than the second portion, and concentration of the second impurity of the first portion and the third portion is greater than concentration of the second impurity of the second portion.

Abstract translation: 半导体器件包括：第一阱，其布置在衬底中并且包括第一导电类型的第一杂质;第二阱，设置在衬底中，包括不同于第一导电类型的第二导电类型的第二杂质，并且首先 第三部分和形成在第一阱和第二阱上的栅极结构，其中第二部分设置在第一部分和第三部分之间，第一部分和第三部分形成得比第二部分更深，并且浓度 第一部分和第三部分的第二杂质大于第二部分的第二杂质的浓度。