公开(公告)号：US09954057B2

公开(公告)日：2018-04-24

申请号：US15424406

申请日：2017-02-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwan-Jae Song ,  Jae-Hyun Yoo ,  In-Hack Lee ,  Seong-Hun Jang ,  Myoung-Kyu Park ,  Young-Mok Kim

IPC: H01L21/00 ,  H01L29/06 ,  H01L21/266 ,  H01L21/308 ,  H01L21/762 ,  H01L29/10 ,  H01L29/78 ,  H01L29/165 ,  H01L29/08

CPC classification number: H01L29/0649 ,  H01L21/266 ,  H01L21/308 ,  H01L21/7624 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/7833

Abstract: A semiconductor device having a high and stable operating voltage and a method of manufacturing the same, the semiconductor device including: a substrate having an active region including a channel region; a gate insulating layer that covers a top surface of the active region; a gate electrode that covers the gate insulating layer on the top surface of the active region; buried insulating patterns in the channel region of the active region at a lower side of the gate electrode and spaced apart from a top surface of the substrate; and a pair of source/drain regions in the substrate at both sides of each of the buried insulating patterns and extending from the top surface of the substrate to a level lower than that of each of the buried insulating patterns.

公开(公告)号：US09941280B2

公开(公告)日：2018-04-10

申请号：US15228292

申请日：2016-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwan-Young Kim ,  Jae-Hyun Yoo ,  Jin-Hyun Noh ,  Woo-Yeol Maeng ,  Yong-Woo Jeon

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/08 ,  H01L23/528

CPC classification number: H01L27/0886 ,  H01L23/528 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0865 ,  H01L29/0873 ,  H01L29/0882 ,  H01L29/4232 ,  H01L29/4236 ,  H01L29/7816 ,  H01L29/7835 ,  H01L29/785

Abstract: According to example embodiments, a semiconductor device includes a first fin, a second fin that is separated from the first fin, and a gate on the first fin and the second fin. The gate crosses the first fin and the second fin. The first fin includes a first doped area at both sides of the gate. The first doped area is configured to have a first voltage applied thereto. The second fin includes a second doped area at both sides of the gate. The second doped area is configured to have a second voltage applied thereto. The second voltage is different than the first voltage.

公开(公告)号：US11699375B1

公开(公告)日：2023-07-11

申请号：US17968407

申请日：2022-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hiroki Fujii ,  Jae-Hyun Yoo

IPC: G09G3/20 ,  H01L29/10

CPC classification number: G09G3/20 ,  H01L29/1041 ,  G09G2310/0291

Abstract: A semiconductor device includes a semiconductor substrate including an active region defined in a well impurity layer having a first conductivity type, a gate electrode on the active region, and a gate insulating layer between the gate electrode and the active region. The active region includes a source region and a drain region at sides of the gate electrode, the source region and the drain region having a second conductivity type, a channel region between the source and drain regions, the channel region having the first conductivity type, a first halo region in contact with the source region and a second halo region in contact with the drain region, the first halo region and the second halo region having the first conductivity type, and a slit well region between the first and second halo regions, the slit well region having the first conductivity type.

公开(公告)号：US10084079B2

公开(公告)日：2018-09-25

申请号：US15052177

申请日：2016-02-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hyun Yoo ,  Kwan-Young Kim ,  Jin-Hyun Noh ,  Kee-Moon Chun ,  Yong-Woo Jeon

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7816 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/66795 ,  H01L29/7835 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor device includes a first well disposed in a substrate and including a first impurity of a first conductivity type, a second well disposed in the substrate, including a second impurity of a second conductivity type different from the first conductivity type, and having first to third portions, and a gate structure formed on the first well and the second well, wherein the second portion is disposed between the first portion and the third portion, the first portion and the third portion are formed deeper than the second portion, and concentration of the second impurity of the first portion and the third portion is greater than concentration of the second impurity of the second portion.

公开(公告)号：US10056479B2

公开(公告)日：2018-08-21

申请号：US14993108

申请日：2016-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Hyun Yoo ,  Jin-Hyun Noh ,  Kee-Moon Chun ,  Jong-Sung Jeon

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/165

CPC classification number: H01L29/7816 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/165 ,  H01L29/7835 ,  H01L29/7848 ,  H01L29/7851

Abstract: A semiconductor device has reduced ON resistance (Ron) as well as a reduced electric field emanating from a current path. The semiconductor device includes a fin pattern, a gate electrode intersecting the fin pattern, a source region which has a first conductivity type and is disposed on one side of the gate electrode, a body region which has a second conductivity type, is situated within the fin pattern under the source region, and extends in a loop around the source region, a drain region which has the first conductivity type and is disposed on the other side of the gate electrode, a field dispersion region which has the second conductivity type and is situated within the fin pattern between the gate electrode and the drain region, and a drift region which has the first conductivity type, is situated within the fin pattern under the drain region and the field dispersion region, and extends in a loop around the drain region and the field dispersion region.

公开(公告)号：US09899541B2

公开(公告)日：2018-02-20

申请号：US14714405

申请日：2015-05-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hyun Yoo

IPC: H01L23/62 ,  H01L29/866 ,  H01L27/02 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/866 ,  H01L27/0255 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/66106

Abstract: Provided are semiconductor devices. A semiconductor device includes a first well formed in a substrate; an element isolation layer formed on the first well; a second well formed in the first well on a first side of the element isolation layer; a third well formed in the second well, the third well has a higher concentration of impurities than the second well; a first electrode electrically connected to the third well; a fourth well formed in the first well on a second side of the element isolation layer; a fifth well formed in the fourth well, the fifth well has a different conductivity type from the fourth well; a second electrode electrically connected to the fifth well; and a sixth well overlapping the fourth well, the sixth well has a lower concentration of impurities than the fourth well.

公开(公告)号：US12068367B2

公开(公告)日：2024-08-20

申请号：US17581026

申请日：2022-01-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jun Hyeok Kim ,  Jae-Hyun Yoo ,  Ui Hui Kwon ,  Kyu Ok Lee ,  Yong Woo Jeon ,  Da Won Jeong

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L29/42376 ,  H01L29/7816

Abstract: A semiconductor device includes a substrate, a gate electrode disposed on an upper surface of the substrate, a source region disposed on a first side of the gate electrode, a drain region disposed on a second side of the gate electrode opposite to the first side of the gate electrode in a horizontal direction, and an insulating structure at least partially buried inside the substrate on the substrate. The insulating structure includes a first portion disposed between the substrate and the gate electrode, and a second portion in contact with the drain region. An uppermost surface of the second portion of the insulating structure is lower than an uppermost surface of the first portion of the insulating structure. At least a part of the gate electrode is disposed on the uppermost surface of the second portion of the insulating structure.

公开(公告)号：US20220406891A1

公开(公告)日：2022-12-22

申请号：US17581026

申请日：2022-01-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jun Hyeok Kim ,  Jae-Hyun Yoo ,  Ui Hui Kwon ,  Kyu Ok Lee ,  Yong Woo Jeon ,  Da Won Jeong

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/78

Abstract: A semiconductor device includes a substrate, a gate electrode disposed on an upper surface of the substrate, a source region disposed on a first side of the gate electrode, a drain region disposed on a second side of the gate electrode opposite to the first side of the gate electrode in a horizontal direction, and an insulating structure at least partially buried inside the substrate on the substrate. The insulating structure includes a first portion disposed between the substrate and the gate electrode, and a second portion in contact with the drain region. An uppermost surface of the second portion of the insulating structure is lower than an uppermost surface of the first portion of the insulating structure. At least a part of the gate electrode is disposed on the uppermost surface of the second portion of the insulating structure.

公开(公告)号：US09548401B2

公开(公告)日：2017-01-17

申请号：US14698909

申请日：2015-04-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Hyun Yoo ,  Jin-Hyun Noh ,  Su-Tae Kim ,  Byeong-Ryeol Lee ,  Seong-Hun Jang ,  Jong-Sung Jeon

IPC: H01L29/02 ,  H01L29/94 ,  H01L29/78 ,  H01L27/06 ,  H01L29/10

CPC classification number: H01L29/94 ,  H01L27/0629 ,  H01L29/1041 ,  H01L29/7833 ,  H01L29/7838 ,  H01L29/7851

Abstract: A semiconductor device includes a substrate including a first impurity diffusion region having a first doping concentration and at least one second impurity diffusion region having a second doping concentration different from the first doping concentration, the at least one second impurity region being surrounded by the first impurity diffusion region; at least one electrode facing the first impurity diffusion region and the at least one second impurity diffusion region; and at least one insulating layer between the first impurity diffusion region and the at least one electrode, and between the at least one second impurity diffusion region and the at least one electrode.

Abstract translation: 一种半导体器件包括：衬底，其包括具有第一掺杂浓度的第一杂质扩散区域和具有不同于第一掺杂浓度的第二掺杂浓度的至少一个第二杂质扩散区域，所述至少一个第二杂质区域被第一杂质包围 扩散区; 面向所述第一杂质扩散区域和所述至少一个第二杂质扩散区域的至少一个电极; 以及在所述第一杂质扩散区域和所述至少一个电极之间以及所述至少一个第二杂质扩散区域和所述至少一个电极之间的至少一个绝缘层。

公开(公告)号：US09337179B2

公开(公告)日：2016-05-10

申请号：US14674559

申请日：2015-03-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Hyun Yoo

IPC: H01L27/082 ,  H01L29/06 ,  H01L21/331 ,  H01L27/02 ,  H01L27/06 ,  H01L29/866 ,  H01L29/735 ,  H01L29/732 ,  H01L29/10 ,  H01L29/08

CPC classification number: H01L27/0255 ,  H01L27/0259 ,  H01L27/067 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/732 ,  H01L29/735 ,  H01L29/861 ,  H01L29/866

Abstract: An electrostatic discharge (ESD) protection circuit includes a substrate, a semiconductor layer provided on the substrate to have a first conductivity type, a first well provided in a first region of the semiconductor layer to have a second conductivity type, an insulating pattern provided in the first well to cross the first well, and first and second doped regions provided in an upper portion of the first well to have the first conductivity type. The first and second doped regions may be laterally spaced apart from each other with the insulating pattern interposed therebetween.

Abstract translation: 静电放电（ESD）保护电路包括基板，设置在基板上以具有第一导电类型的半导体层，设置在半导体层的第一区域中以具有第二导电类型的第一阱，设置在 第一阱穿过第一阱，以及设置在第一阱的上部中的第一和第二掺杂区域以具有第一导电类型。 第一和第二掺杂区域可以彼此横向间隔开，绝缘图案插入其间。