公开(公告)号：US11989142B2

公开(公告)日：2024-05-21

申请号：US17586767

申请日：2022-01-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Marie Mai Nguyen ,  Rekha Pitchumani ,  Zongwang Li ,  Yang Seok Ki ,  Krishna Teja Malladi

IPC: G06F12/02 ,  G06F13/16

CPC classification number: G06F13/1668

Abstract: An accelerator is disclosed. A circuit may process a data to produce a processed data. A first tier storage may include a first capacity and a first latency. A second tier storage may include a second capacity and a second latency. The second capacity may be larger than the first capacity, and the second latency may be slower than the first latency. A bus may be used to transfer at least one of the data or the processed data between the first tier storage and the second tier storage.

公开(公告)号：US11841814B2

公开(公告)日：2023-12-12

申请号：US17887379

申请日：2022-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Krishna Teja Malladi ,  Andrew Chang ,  Ehsan M. Najafabadi

IPC: G06F13/40 ,  G06F3/06 ,  G06F9/4401 ,  G06F12/0802 ,  G06F12/0808 ,  G06F12/1045 ,  G06F13/16 ,  G06F15/173 ,  G06F13/42 ,  G06F13/28 ,  H04L49/45 ,  H04L49/351

CPC classification number: G06F13/4027 ,  G06F3/0604 ,  G06F3/067 ,  G06F3/0619 ,  G06F3/0625 ,  G06F3/0629 ,  G06F3/0647 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0679 ,  G06F9/4401 ,  G06F12/0802 ,  G06F12/0808 ,  G06F12/1045 ,  G06F13/1663 ,  G06F13/28 ,  G06F13/409 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4221 ,  G06F15/17331 ,  H04L49/45 ,  G06F2212/621 ,  G06F2213/0026 ,  G06F2213/28 ,  H04L49/351

Abstract: A system and method for managing memory resources. In some embodiments the system includes a first server, a second server, and a server-linking switch connected to the first server and to the second server. The first server may include a stored-program processing circuit, a cache-coherent switch, and a first memory module. In some embodiments, the first memory module is connected to the cache-coherent switch, the cache-coherent switch is connected to the server-linking switch, and the stored-program processing circuit is connected to the cache-coherent switch.

公开(公告)号：US11416431B2

公开(公告)日：2022-08-16

申请号：US17026074

申请日：2020-09-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Krishna Teja Malladi ,  Andrew Chang ,  Ehsan M. Najafabadi

IPC: G06F13/40 ,  G06F3/06 ,  G06F9/4401 ,  G06F12/0802 ,  G06F12/0808 ,  G06F12/1045 ,  G06F13/16 ,  G06F15/173 ,  G06F13/42 ,  G06F13/28 ,  H04L49/45 ,  H04L49/351

Abstract: A system and method for managing memory resources. In some embodiments the system includes a first server, a second server, and a server-linking switch connected to the first server and to the second server. The first server may include a stored-program processing circuit, a cache-coherent switch, and a first memory module. In some embodiments, the first memory module is connected to the cache-coherent switch, the cache-coherent switch is connected to the server-linking switch, and the stored-program processing circuit is connected to the cache-coherent switch.

公开(公告)号：US20210311871A1

公开(公告)日：2021-10-07

申请号：US17026082

申请日：2020-09-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Krishna Teja Malladi ,  Andrew Chang ,  Byung Hee Choi ,  Ehsan M. Najafabadi

IPC: G06F12/0802 ,  G06F13/28 ,  H04L12/931

Abstract: A system and method for managing memory resources. In some embodiments, the system includes a stored-program processing circuit, a network interface circuit, a cache-coherent switch, and a first memory module. In some embodiments, the first memory module is connected to the cache-coherent switch, the cache-coherent switch is connected to the network interface circuit, and the stored-program processing circuit is connected to the cache-coherent switch.

公开(公告)号：US20240045823A1

公开(公告)日：2024-02-08

申请号：US18381571

申请日：2023-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Krishna Teja Malladi ,  Andrew Chang ,  Ehsan M. Najafabadi

IPC: G06F13/40 ,  G06F15/173 ,  G06F9/4401 ,  G06F3/06 ,  G06F12/0808 ,  G06F12/1045 ,  G06F13/16 ,  G06F13/42 ,  G06F12/0802 ,  G06F13/28 ,  H04L49/45

CPC classification number: G06F13/4027 ,  G06F15/17331 ,  G06F9/4401 ,  G06F13/4022 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/0625 ,  G06F3/0629 ,  G06F3/0647 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/067 ,  G06F3/0679 ,  G06F12/0808 ,  G06F12/1045 ,  G06F13/1663 ,  G06F13/4068 ,  G06F13/409 ,  G06F13/4221 ,  G06F12/0802 ,  G06F13/28 ,  H04L49/45 ,  G06F2213/0026 ,  G06F2212/621 ,  G06F2213/28 ,  H04L49/351

Abstract: A system and method for managing memory resources. In some embodiments the system includes a first server, a second server, and a server-linking switch connected to the first server and to the second server. The first server may include a stored-program processing circuit, a cache-coherent switch, and a first memory module. In some embodiments, the first memory module is connected to the cache-coherent switch, the cache-coherent switch is connected to the server-linking switch, and the stored-program processing circuit is connected to the cache-coherent switch.

公开(公告)号：US20220382702A1

公开(公告)日：2022-12-01

申请号：US17887379

申请日：2022-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Krishna Teja Malladi ,  Andrew Chang ,  Ehsan M. Najafabadi

IPC: G06F13/40 ,  G06F15/173 ,  G06F9/4401 ,  G06F3/06 ,  G06F12/0808 ,  G06F12/1045 ,  G06F13/16 ,  G06F13/42 ,  G06F12/0802 ,  G06F13/28 ,  H04L49/45

Abstract: A system and method for managing memory resources. In some embodiments the system includes a first server, a second server, and a server-linking switch connected to the first server and to the second server. The first server may include a stored-program processing circuit, a cache-coherent switch, and a first memory module. In some embodiments, the first memory module is connected to the cache-coherent switch, the cache-coherent switch is connected to the server-linking switch, and the stored-program processing circuit is connected to the cache-coherent switch.

公开(公告)号：US11461263B2

公开(公告)日：2022-10-04

申请号：US17026087

申请日：2020-09-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Krishna Teja Malladi ,  Byung Hee Choi ,  Andrew Chang ,  Ehsan M. Najafabadi

IPC: G06F13/40 ,  G06F15/173 ,  G06F9/4401 ,  G06F3/06 ,  G06F12/0808 ,  G06F12/1045 ,  G06F13/16 ,  G06F13/42 ,  G06F12/0802 ,  G06F13/28 ,  H04L49/45 ,  H04L49/351

Abstract: A system and method for managing memory resources. In some embodiments, the system includes a first memory server, a second memory server, and a server-linking switch connected to the first memory server and to the second memory server. The first server may include a cache-coherent switch and a first memory module. In some embodiments, the first memory module is connected to the cache-coherent switch, and the cache-coherent switch is connected to the server-linking switch.

公开(公告)号：US20210311900A1

公开(公告)日：2021-10-07

申请号：US17026074

申请日：2020-09-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Krishna Teja Malladi ,  Andrew Chang ,  Ehsan M. Najafabadi

IPC: G06F13/40 ,  G06F9/4401 ,  G06F15/173

Abstract: A system and method for managing memory resources. In some embodiments the system includes a first server, a second server, and a server-linking switch connected to the first server and to the second server. The first server may include a stored-program processing circuit, a cache-coherent switch, and a first memory module. In some embodiments, the first memory module is connected to the cache-coherent switch, the cache-coherent switch is connected to the server-linking switch, and the stored-program processing circuit is connected to the cache-coherent switch.

公开(公告)号：US12197350B2

公开(公告)日：2025-01-14

申请号：US17586770

申请日：2022-01-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Marie Mai Nguyen ,  Rekha Pitchumani ,  Yang Seok Ki ,  Krishna Teja Malladi

IPC: G06F13/16 ,  G06F9/30 ,  G06F13/42

Abstract: An accelerator is disclosed. A tier storage may store data. A circuit may process the data to produce a processed data. The accelerator may load the data from a device using a cache-coherent interconnect protocol.

公开(公告)号：US11940934B2

公开(公告)日：2024-03-26

申请号：US17586767

申请日：2022-01-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Marie Mai Nguyen ,  Rekha Pitchumani ,  Zongwang Li ,  Yang Seok Ki ,  Krishna Teja Malladi

IPC: G06F12/02 ,  G06F13/16

CPC classification number: G06F13/1668

Abstract: An accelerator is disclosed. A circuit may process a data to produce a processed data. A first tier storage may include a first capacity and a first latency. A second tier storage may include a second capacity and a second latency. The second capacity may be larger than the first capacity, and the second latency may be slower than the first latency. A bus may be used to transfer at least one of the data or the processed data between the first tier storage and the second tier storage.