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公开(公告)号:US20230148191A1
公开(公告)日:2023-05-11
申请号:US18094794
申请日:2023-01-09
Applicant: Samsung Electronics Co., Ltd.
Inventor: NAMHOON KIM , SEUNGHOON YEON , YONGHOE CHO
IPC: H01L23/00
CPC classification number: H01L24/20 , H01L24/13 , H01L2224/214 , H01L2224/2101
Abstract: Disclosed is a semiconductor package comprising a redistribution substrate, a semiconductor chip on the redistribution substrate and including a chip pad electrically connected to the redistribution substrate, and a conductive terminal on the redistribution substrate. The redistribution substrate includes a first dielectric layer, a first redistribution pattern, a second dielectric layer, a second redistribution pattern, and a first insulative pattern. The first redistribution pattern electrically connects the chip pad and the second redistribution pattern. The first insulative pattern has a first surface in contact with the first redistribution pattern and a second surface in contact with the second redistribution pattern. The second surface is opposite to the first surface. A width at the first surface of the first insulative pattern is the same as or greater than a width at the second surface of the first insulative pattern.
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公开(公告)号:US20210157762A1
公开(公告)日:2021-05-27
申请号:US16924428
申请日:2020-07-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: JEAYOUNG KWON , KYUNGHUN KIM , NAMHOON KIM
Abstract: A portable storage device includes nonvolatile memory devices to store data, a storage controller, and a bridge chipset. The bridge chipset is connected to a first connector of a host through a cable assembly, detects a resistance of the cable assembly, provides the storage controller with USB type information of the first connector based on the detected resistance, and after a USB connection is established with the host, provides the storage controller with USB version information associated with the established USB connection. The storage controller selects one of a plurality of initializing modes based on the USB type information and the USB version information, selects clock signals having frequencies in a range within a maximum power level, and performs an initializing operation based on the selected clock signals within an internal reference time interval.
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公开(公告)号:US20240021663A1
公开(公告)日:2024-01-18
申请号:US18213473
申请日:2023-06-23
Applicant: Samsung Electronics Co., Ltd.
Inventor: SOOJAE PARK , NAMHOON KIM , JONGHYUN LEE , CHUL-HYUNG CHO
Abstract: A wire capacitor includes a wire structure extending in a longitudinal direction and a conductive layer covering an outer surface of the wire structure. The wire structure includes a core electrode line having a wire shape and extending in the longitudinal direction and a dielectric line surrounding an outer surface of the core electrode line and extending in the longitudinal direction. The wire structure has a first end and a second end which are opposite to each other in the longitudinal direction, and the conductive layer exposes an outer circumference of the first end and the second end of the wire structure.
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公开(公告)号:US20220165696A1
公开(公告)日:2022-05-26
申请号:US17350708
申请日:2021-06-17
Applicant: Samsung Electronics Co., Ltd.
Inventor: NAMHOON KIM
IPC: H01L23/00 , H01L25/065 , H01L23/48
Abstract: A semiconductor package comprising a package substrate that has a recessed portion on a top surface thereof, a lower semiconductor chip in the recessed portion of the package substrate, an upper semiconductor chip on the lower semiconductor chip and the package substrate and having a width greater than that of the lower semiconductor chip, a plurality of first bumps directly between the package substrate and the upper semiconductor chip, and a plurality of second bumps directly between the lower semiconductor chip and the upper semiconductor chip. A pitch of the second bumps is less than that of the first bumps.
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公开(公告)号:US20230215842A1
公开(公告)日:2023-07-06
申请号:US18120587
申请日:2023-03-13
Applicant: Samsung Electronics Co., Ltd.
Inventor: NAMHOON KIM , CHAJEA JO , Ohguk KWON , HYOEUN KIM , SEUNGHOON YEON
IPC: H01L25/065 , H01L23/00
CPC classification number: H01L25/0657 , H01L25/0652 , H01L24/02 , H01L2225/06513 , H01L2924/18161 , H01L2225/06586 , H01L2225/06589 , H01L2224/02372 , H01L2225/06541
Abstract: A semiconductor package includes a first semiconductor chip comprising a semiconductor substrate and a redistribution pattern on a top surface of the semiconductor substrate, the redistribution pattern having a hole exposing an inner sidewall of the redistribution pattern, a second semiconductor chip on a top surface of the first semiconductor chip, and a bump structure disposed between the first semiconductor chip and the second semiconductor chip. The bump structure is disposed in the hole and is in contact with the inner sidewall of the redistribution pattern.
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公开(公告)号:US20220037279A1
公开(公告)日:2022-02-03
申请号:US17193435
申请日:2021-03-05
Applicant: Samsung Electronics Co., Ltd.
Inventor: NAMHOON KIM , SEUNGHOON YEON , YONGHOE CHO
IPC: H01L23/00
Abstract: Disclosed is a semiconductor package comprising a redistribution substrate, a semiconductor chip on the redistribution substrate and including a chip pad electrically connected to the redistribution substrate, and a conductive terminal on the redistribution substrate. The redistribution substrate includes a first dielectric layer, a first redistribution pattern, a second dielectric layer, a second redistribution pattern, and a first insulative pattern. The first redistribution pattern electrically connects the chip pad and the second redistribution pattern. The first insulative pattern has a first surface in contact with the first redistribution pattern and a second surface in contact with the second redistribution pattern. The second surface is opposite to the first surface. A width at the first surface of the first insulative pattern is the same as or greater than a width at the second surface of the first insulative pattern.
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公开(公告)号:US20240297139A1
公开(公告)日:2024-09-05
申请号:US18646951
申请日:2024-04-26
Applicant: Samsung Electronics Co., Ltd.
Inventor: NAMHOON KIM
IPC: H01L23/00 , H01L23/48 , H01L25/065
CPC classification number: H01L24/16 , H01L23/481 , H01L24/04 , H01L24/17 , H01L24/32 , H01L24/33 , H01L24/73 , H01L25/0652 , H01L25/0657 , H01L2224/02372 , H01L2224/0401 , H01L2224/16146 , H01L2224/16227 , H01L2224/1703 , H01L2224/17132 , H01L2224/17181 , H01L2224/17183 , H01L2224/32225 , H01L2224/33181 , H01L2224/33183 , H01L2224/73204 , H01L2225/06513 , H01L2225/06517
Abstract: A semiconductor package comprising a package substrate that has a recessed portion on a top surface thereof, a lower semiconductor chip in the recessed portion of the package substrate, an upper semiconductor chip on the lower semiconductor chip and the package substrate and having a width greater than that of the lower semiconductor chip, a plurality of first bumps directly between the package substrate and the upper semiconductor chip, and a plurality of second bumps directly between the lower semiconductor chip and the upper semiconductor chip. A pitch of the second bumps is less than that of the first bumps.
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公开(公告)号:US20220013501A1
公开(公告)日:2022-01-13
申请号:US17178327
申请日:2021-02-18
Applicant: Samsung Electronics Co., Ltd.
Inventor: NAMHOON KIM , CHAJEA JO , Ohguk KWON , HYOEUN KIM , SEUNGHOON YEON
IPC: H01L25/065 , H01L23/00
Abstract: A semiconductor package includes a first semiconductor chip comprising a semiconductor substrate and a redistribution pattern on a top surface of the semiconductor substrate, the redistribution pattern having a hole exposing an inner sidewall of the redistribution pattern, a second semiconductor chip on a top surface of the first semiconductor chip, and a bump structure disposed between the first semiconductor chip and the second semiconductor chip. The bump structure is disposed in the hole and is in contact with the inner sidewall of the redistribution pattern.
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