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    Clock data recovery circuit and apparatus including the same
    1.
    发明授权
    Clock data recovery circuit and apparatus including the same 有权

    公开(公告)号：US12155743B2

    公开(公告)日：2024-11-26

    申请号：US17957414

    申请日：2022-09-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sunggeun Kim ,  Nakwon Lee ,  Jaehyun Park ,  Kyeongjoon Ko ,  Kangjik Kim ,  Seuk Son ,  Byunghyun Lim

    IPC: H04L7/00

    Abstract: A clock data recovery circuit includes an inphase-quadrature (I-Q) merged phase interpolator circuit configured to generate a first clock pair and a second clock pair from a plurality of reference clock signals, the plurality of reference clock signals having different phases, the first clock pair comprising an I clock signal and an inverted I clock signal, and the second clock pair comprising a Q clock signal and an inverted Q clock signal, a sampler circuit configured to sample input data based on the first clock pair and the second clock pair, and a control circuit configured to control phases of the first clock pair and the second clock pair, the controlling including providing a control signal to the I-Q merged phase interpolator circuit based on a sampling result of the sampler circuit, the I-Q merged phase interpolator circuit is configured to share analog inputs based on the control signal.

    INTEGRATED CIRCUIT INCLUDING HIGH-SPEED DEVICE
    2.
    发明申请
    INTEGRATED CIRCUIT INCLUDING HIGH-SPEED DEVICE 有权

    公开(公告)号：US20220399266A1

    公开(公告)日：2022-12-15

    申请号：US17837786

    申请日：2022-06-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Gyeongseok Song ,  Kyeongjoon Ko ,  Jaehyun Park ,  Junhan Bae ,  Jongjae Ryu ,  Nakwon Lee

    IPC: H01L23/528 ,  H01L27/088

    Abstract: An integrated circuit is provided. The integrated circuit includes: an active region extending in a first direction; gate electrodes extending in a second direction in parallel with each other; source/drain regions provided on the active region between the gate electrodes; a first gate contact connected to the gate electrodes and extending in the first direction; a first gate wiring pattern provided in a first wiring layer, electrically connected to the gate electrodes through the first gate contact, and overlapping the first gate contact along a third direction perpendicular to the first and second directions; and source/drain wiring patterns provided in a second wiring layer, electrically connected to the source/drain regions, respectively, extending in parallel with the second direction, and overlapping the source/drain regions along the third direction, the second wiring layer being provided on the first wiring layer.

    Monotonic and glitch-free phase interpolator and communication device including the same
    3.
    发明授权
    Monotonic and glitch-free phase interpolator and communication device including the same 有权

    公开(公告)号：US11757437B2

    公开(公告)日：2023-09-12

    申请号：US17463617

    申请日：2021-09-01

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seuk Son ,  Hobin Song ,  Nakwon Lee

    IPC: H03K5/13 ,  H03K5/01 ,  H03K19/21 ,  G06F1/06 ,  H03M7/16 ,  H03K5/00

    CPC classification number: H03K5/01 ,  G06F1/06 ,  H03K19/21 ,  H03M7/165 ,  H03K2005/00058

    Abstract: A phase interpolator includes a decoder, a digital-to-analog converter (DAC), and a phase mixer. The decoder generates first and second thermometer codes and a selection signal based on a code. The DAC includes unit cells, determines two of weight signals as first and second target weight signals based on the selection signal, and adjusts a current of the first and second target weight signals by controlling the unit cells based on the first and second thermometer codes and the selection signal. The phase mixer determines two of input clock signals as first and second target clock signals and generates an output clock signal based on the first and second target weight signals and the first and second target clock signals. A phase of the output clock signal is between phases of the first and second target clock signals. The unit cells include different first and second unit cells.

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