公开(公告)号：US20210028112A1

公开(公告)日：2021-01-28

申请号：US16863126

申请日：2020-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinnam Kim ,  Kwangjin Moon ,  Hojin Lee ,  Pilkyu Kang ,  Hoonjoo Na

IPC: H01L23/535 ,  H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L29/417 ,  H01L23/48 ,  H01L21/768 ,  H01L29/66

Abstract: A semiconductor device includes a substrate having a first surface and a second surface opposite to each other, and having an active region located on the first surface and defined by a first isolation region; a plurality of active fins arranged on the active region, extending in a first direction, and defined by a second isolation region having a second depth smaller than a first depth of the first isolation region; a buried conductive wiring in a trench adjacent to the plurality of active fins, and extending in a direction of the trench; a filling insulation portion in the trench, and having the buried conductive wiring therein; an interlayer insulation layer on the first and second isolation regions and on the buried conductive wiring; a contact structure penetrating the interlayer insulation layer, and contacting the buried conductive wiring; and a conductive through structure extending through the substrate from the second surface to the trench, and contacting the buried conductive wiring.

公开(公告)号：US11955408B2

公开(公告)日：2024-04-09

申请号：US17036145

申请日：2020-09-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sohye Cho ,  Pilkyu Kang ,  Kwangjin Moon ,  Taeseong Kim

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/50 ,  H01L23/528 ,  H10B10/00

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/5286 ,  H10B10/12 ,  H01L23/50

Abstract: An integrated circuit semiconductor device includes a substrate including a first surface and a second surface opposite the first surface, a trench in the substrate, the trench extending from the first surface of the substrate toward the second surface of the substrate, a through silicon via (TSV) landing part in the trench, the TSV landing part having a first portion spaced apart from the first surface of the substrate, and a second portion between the first portion and the first surface of the substrate, the first portion being wider than the second portion, a TSV hole in the substrate, the TSV hole extending from the second surface of the substrate and aligned with a bottom surface of the TSV landing part, and a TSV in the TSV hole and in contact with the bottom surface of the TSV landing part.

公开(公告)号：US11362067B2

公开(公告)日：2022-06-14

申请号：US16855352

申请日：2020-04-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyuha Lee ,  Pilkyu Kang ,  Seokho Kim ,  Hoonjoo Na ,  Kwangjin Moon ,  Jaehyung Park ,  Joohee Jang ,  Yikoan Hong

IPC: H01L25/065 ,  H01L23/00

Abstract: A method of manufacturing a semiconductor device according to example embodiments includes: sequentially forming first through third insulating layers on a substrate; forming an opening by etching the first through third insulating layers; forming a conductive layer configured in the opening; forming a fourth insulating layer in the opening after the forming of the conductive layer; and removing a portion of an edge region of the substrate after the forming of the fourth insulating layer.

公开(公告)号：US11721628B2

公开(公告)日：2023-08-08

申请号：US16863126

申请日：2020-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinnam Kim ,  Kwangjin Moon ,  Hojin Lee ,  Pilkyu Kang ,  Hoonjoo Na

IPC: H01L23/535 ,  H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L23/48 ,  H01L23/528 ,  H01L23/485 ,  H01L21/768

CPC classification number: H01L23/535 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76895 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/485 ,  H01L23/5286 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device includes a substrate having a first surface and a second surface opposite to each other, and having an active region located on the first surface and defined by a first isolation region; a plurality of active fins arranged on the active region, extending in a first direction, and defined by a second isolation region having a second depth smaller than a first depth of the first isolation region; a buried conductive wiring in a trench adjacent to the plurality of active fins, and extending in a direction of the trench; a filling insulation portion in the trench, and having the buried conductive wiring therein; an interlayer insulation layer on the first and second isolation regions and on the buried conductive wiring; a contact structure penetrating the interlayer insulation layer, and contacting the buried conductive wiring; and a conductive through structure extending through the substrate from the second surface to the trench, and contacting the buried conductive wiring.

公开(公告)号：US11177286B2

公开(公告)日：2021-11-16

申请号：US16807410

申请日：2020-03-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Weonhong Kim ,  Pilkyu Kang ,  Yuichiro Sasaki ,  Sungkeun Lim ,  Yongho Ha ,  Sangjin Hyun ,  Kughwan Kim ,  Seungha Oh

IPC: H01L27/12 ,  H01L29/78 ,  H01L21/762 ,  H01L27/02

Abstract: An integrated circuit device includes an embedded insulation layer, a semiconductor layer on the embedded insulation layer, the semiconductor layer having a main surface, and a plurality of fin-type active areas protruding from the main surface to extend in a first horizontal direction and in parallel with one another, a separation insulation layer separating the semiconductor layer into at least two element regions adjacent to each other in a second horizontal direction intersecting the first horizontal direction, source/drain regions on the plurality of fin-type active areas, a first conductive plug on and electrically connected to the source/drain regions, a buried rail electrically connected to the first conductive plug while penetrating through the separation insulation layer and the semiconductor layer, and a power delivery structure arranged in the embedded insulation layer, the power delivery structure being in contact with and electrically connected to the buried rail.

公开(公告)号：US20230352410A1

公开(公告)日：2023-11-02

申请号：US18347512

申请日：2023-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinnam Kim ,  Kwangjin Moon ,  Hojin Lee ,  Pilkyu Kang ,  Hoonjoo Na

IPC: H01L23/535 ,  H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L21/768 ,  H01L23/48 ,  H01L23/528 ,  H01L23/485

CPC classification number: H01L23/535 ,  H01L29/7851 ,  H01L29/0847 ,  H01L29/0653 ,  H01L29/41791 ,  H01L29/66795 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76895 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5286 ,  H01L23/485

Abstract: A semiconductor device includes a substrate having a first and second surface opposite to each other, and an active region on the first surface and defined by a first isolation region; a plurality of active fins on the active region, extending in a first direction, and defined by a second isolation region having a second depth smaller than a first depth of the first isolation region; a buried conductive wiring in a trench adjacent to the fins, and extending in a direction of the trench; a filling insulation portion in the trench, and having the wiring therein; an interlayer insulation layer on the first and second isolation regions and on the buried conductive wiring; a contact structure penetrating the interlayer insulation layer, and contacting the buried conductive wiring; and a conductive through structure extending through the substrate from the second surface to the trench, and contacting the buried conductive wiring.

公开(公告)号：US11728347B2

公开(公告)日：2023-08-15

申请号：US17494275

申请日：2021-10-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Weonhong Kim ,  Pilkyu Kang ,  Yuichiro Sasaki ,  Sungkeun Lim ,  Yongho Ha ,  Sangjin Hyun ,  Kughwan Kim ,  Seungha Oh

IPC: H01L27/12 ,  H01L21/762 ,  H01L27/02 ,  H01L29/78

CPC classification number: H01L27/1203 ,  H01L21/76224 ,  H01L27/0203 ,  H01L27/02 ,  H01L29/78

Abstract: An integrated circuit device includes an embedded insulation layer, a semiconductor layer on the embedded insulation layer, the semiconductor layer having a main surface, and a plurality of fin-type active areas protruding from the main surface to extend in a first horizontal direction and in parallel with one another, a separation insulation layer separating the semiconductor layer into at least two element regions adjacent to each other in a second horizontal direction intersecting the first horizontal direction, source/drain regions on the plurality of fin-type active areas, a first conductive plug on and electrically connected to the source/drain regions, a buried rail electrically connected to the first conductive plug while penetrating through the separation insulation layer and the semiconductor layer, and a power delivery structure arranged in the embedded insulation layer, the power delivery structure being in contact with and electrically connected to the buried rail.

公开(公告)号：US20210066250A1

公开(公告)日：2021-03-04

申请号：US16855352

申请日：2020-04-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyuha Lee ,  Pilkyu Kang ,  Seokho Kim ,  Hoonjoo Na ,  Kwangjin Moon ,  Jaehyung Park ,  Joohee Jang ,  Yikoan Hong

IPC: H01L25/065 ,  H01L23/00

Abstract: A method of manufacturing a semiconductor device according to example embodiments includes: sequentially forming first through third insulating layers on a substrate; forming an opening by etching the first through third insulating layers; forming a conductive layer configured in the opening; forming a fourth insulating layer in the opening after the forming of the conductive layer; and removing a portion of an edge region of the substrate after the forming of the fourth insulating layer.