公开(公告)号：US20130260551A1

公开(公告)日：2013-10-03

申请号：US13903164

申请日：2013-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Un-Byoung Kang ,  Kwang-chul Choi ,  Jung-Hwan Kim ,  Tae Hong Min ,  Hojin Lee ,  Minseung Yoon

IPC: H01L21/48

CPC classification number: H01L21/4835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0657 ,  H01L27/14618 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02166 ,  H01L2224/02313 ,  H01L2224/02372 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/024 ,  H01L2224/03462 ,  H01L2224/03466 ,  H01L2224/03602 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05026 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/06131 ,  H01L2224/06135 ,  H01L2224/06138 ,  H01L2224/06181 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/16147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29011 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: In a semiconductor device, an organic insulation pattern is disposed between first and second rerouting patterns. The organic insulation pattern may absorb the physical stress that occurs when the first and second rerouting patterns expand under heat. Since the organic insulation pattern is disposed between the first and second rerouting patterns, insulating properties can be increased relative to a semiconductor device in which a semiconductor pattern is disposed between rerouting patterns. Also, since a seed layer pattern is disposed between the first and second rerouting patterns and the organic insulation pattern and between the substrate and the organic insulation pattern, the adhesive strength of the first and second rerouting patterns is enhanced. This also reduces any issues with delamination. Also, the seed layer pattern prevents the metal that forms the rerouting pattern from being diffused to the organic insulation pattern. Therefore, a semiconductor device with enhanced reliability may be implemented.

Abstract translation: 在半导体器件中，有机绝缘图案设置在第一和第二重新布线图案之间。 有机绝缘图案可以吸收当第一和第二重新布线图案在加热下膨胀时发生的物理应力。 由于有机绝缘图案设置在第一和第二重新布线图案之间，所以可以相对于其中在重新布线图案之间设置半导体图案的半导体器件来增加绝缘性能。 此外，由于在第一和第二重新布线图案和有机绝缘图案之间以及基板和有机绝缘图案之间设置种子层图案，所以第一和第二布线图案的粘合强度提高。 这也减少了分层问题。 此外，种子层图案防止形成重新布线图案的金属扩散到有机绝缘图案。 因此，可以实现具有增强的可靠性的半导体器件。

公开(公告)号：US11965674B2

公开(公告)日：2024-04-23

申请号：US17235340

申请日：2021-04-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Juwan Park ,  Nakhyun Kim ,  Juyoung Kim ,  Changhyun Park ,  Moonsun Shin ,  Wonhee Lee ,  Hojin Lee ,  Changwoo Jung

IPC: F24F8/10 ,  F24F8/108 ,  F24F13/20 ,  F24F13/28

CPC classification number: F24F8/108 ,  F24F13/20 ,  F24F13/28

Abstract: An air purifier or air conditioner including a filter device. The air purifier includes: a main body: a suction port provided to allow air to flow into the main body; a filter provided in the main body to filter the air suctioned from the suction port and including a frame and a filter body fixed to the frame; an auxiliary filter member separably mounted on the filter; and a locking device provided on the frame of the filter such that the auxiliary filter member is separably mounted on the frame of the filter.

公开(公告)号：US11908775B2

公开(公告)日：2024-02-20

申请号：US17645472

申请日：2021-12-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaewon Hwang ,  Kwangjin Moon ,  Hojin Lee ,  Hyungjun Jeon

IPC: H01L23/48 ,  H01L23/485 ,  H01L23/535 ,  H01L23/00

CPC classification number: H01L23/485 ,  H01L23/481 ,  H01L23/535 ,  H01L24/29 ,  H01L24/45

Abstract: A semiconductor device includes a semiconductor substrate having a first surface adjacent to an active layer; a first insulating layer disposed on the first surface of the semiconductor substrate; a second insulating layer disposed on the first insulating layer; an etch stop structure interposed between the first insulating layer and the second insulating layer and including a plurality of etch stop layers; a contact wiring pattern disposed inside the second insulating layer and surrounded by at least one etch stop layer of the plurality of etch stop layers; and a through electrode structure configured to pass through the semiconductor substrate, the first insulating layer, and at least one etch stop layer of the plurality of etch stop layers in a vertical direction and contact the contact wiring pattern.

公开(公告)号：US20230139574A1

公开(公告)日：2023-05-04

申请号：US17851289

申请日：2022-06-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUNGGUN YOU ,  Beomjin Park ,  Sughyun Sung ,  Hojin Lee ,  Dongwon Kim ,  Donggyu Lee ,  Myoung-Sun Lee ,  Keun Hwi Cho ,  Hanbyul Choi ,  Jiyong Ha

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/66

Abstract: A semiconductor device includes: an active pattern on a substrate, wherein the active pattern includes a plurality of channel layers stacked on one another; a plurality of source/drain patterns spaced apart from each other in a first direction and disposed on the active pattern, wherein the plurality of source/drain patterns are connected to each other through the plurality of channel layers; and first and second gate electrodes at least partially surrounding the channel layers and extending in a second direction, wherein the second direction intersects the first direction, wherein the active pattern has a first sidewall and a second sidewall that faces the first sidewall, and wherein a first distance between the first sidewall of the active pattern and an outer sidewall of the first gate electrode is different from a second distance between the second sidewall of the active pattern and an outer sidewall of the second gate electrode.

公开(公告)号：US11961788B2

公开(公告)日：2024-04-16

申请号：US17708137

申请日：2022-03-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyoukyung Cho ,  Hojin Lee ,  Kwangjin Moon

IPC: H01L23/48 ,  H01L21/762 ,  H01L21/768 ,  H01L25/065 ,  H01L29/06

CPC classification number: H01L23/481 ,  H01L21/76224 ,  H01L21/76816 ,  H01L21/76898 ,  H01L25/0657 ,  H01L29/0649 ,  H01L2225/06544

Abstract: A semiconductor device includes: a semiconductor substrate having opposing first side and second sides; an active region and an isolation region on the first side; a circuit device on the active region; a front side interconnection structure on the first side and including front side interconnection layers disposed on different levels; first and second back side interconnection structures below the second side; a buried structure having a portion disposed in the isolation region and including a conductive line; a first through-electrode structure including a first through-electrode contacting the conductive line and penetrating the semiconductor substrate between the conductive line and the first back side interconnection structure; and a second through-electrode structure including a second through-electrode penetrating the semiconductor substrate between a first front side interconnection layer and the second back side interconnection structure. The first front side interconnection layer is on a level higher than that of the conductive line.

公开(公告)号：US11721628B2

公开(公告)日：2023-08-08

申请号：US16863126

申请日：2020-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinnam Kim ,  Kwangjin Moon ,  Hojin Lee ,  Pilkyu Kang ,  Hoonjoo Na

IPC: H01L23/535 ,  H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L23/48 ,  H01L23/528 ,  H01L23/485 ,  H01L21/768

CPC classification number: H01L23/535 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76895 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/485 ,  H01L23/5286 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device includes a substrate having a first surface and a second surface opposite to each other, and having an active region located on the first surface and defined by a first isolation region; a plurality of active fins arranged on the active region, extending in a first direction, and defined by a second isolation region having a second depth smaller than a first depth of the first isolation region; a buried conductive wiring in a trench adjacent to the plurality of active fins, and extending in a direction of the trench; a filling insulation portion in the trench, and having the buried conductive wiring therein; an interlayer insulation layer on the first and second isolation regions and on the buried conductive wiring; a contact structure penetrating the interlayer insulation layer, and contacting the buried conductive wiring; and a conductive through structure extending through the substrate from the second surface to the trench, and contacting the buried conductive wiring.

公开(公告)号：US20220359348A1

公开(公告)日：2022-11-10

申请号：US17645472

申请日：2021-12-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaewon Hwang ,  Kwangjin Moon ,  Hojin Lee ,  Hyungjun Jeon

IPC: H01L23/485 ,  H01L23/535 ,  H01L23/48 ,  H01L23/00

Abstract: A semiconductor device includes a semiconductor substrate having a first surface adjacent to an active layer; a first insulating layer disposed on the first surface of the semiconductor substrate; a second insulating layer disposed on the first insulating layer; an etch stop structure interposed between the first insulating layer and the second insulating layer and including a plurality of etch stop layers; a contact wiring pattern disposed inside the second insulating layer and surrounded by at least one etch stop layer of the plurality of etch stop layers; and a through electrode structure configured to pass through the semiconductor substrate, the first insulating layer, and at least one etch stop layer of the plurality of etch stop layers in a vertical direction and contact the contact wiring pattern.

公开(公告)号：US09196505B2

公开(公告)日：2015-11-24

申请号：US13903164

申请日：2013-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Un-Byoung Kang ,  Kwang-Chul Choi ,  Jung-Hwan Kim ,  Tae Hong Min ,  Hojin Lee ,  Minseung Yoon

IPC: H01L21/00 ,  H01L21/48 ,  H01L23/31 ,  H01L23/00 ,  H01L21/768 ,  H01L21/683 ,  H01L25/065 ,  H01L27/146 ,  H01L23/498

CPC classification number: H01L21/4835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0657 ,  H01L27/14618 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02166 ,  H01L2224/02313 ,  H01L2224/02372 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/024 ,  H01L2224/03462 ,  H01L2224/03466 ,  H01L2224/03602 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05026 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/06131 ,  H01L2224/06135 ,  H01L2224/06138 ,  H01L2224/06181 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/16147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29011 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: In a semiconductor device, an organic insulation pattern is disposed between first and second rerouting patterns. The organic insulation pattern may absorb the physical stress that occurs when the first and second rerouting patterns expand under heat. Since the organic insulation pattern is disposed between the first and second rerouting patterns, insulating properties can be increased relative to a semiconductor device in which a semiconductor pattern is disposed between rerouting patterns. Also, since a seed layer pattern is disposed between the first and second rerouting patterns and the organic insulation pattern and between the substrate and the organic insulation pattern, the adhesive strength of the first and second rerouting patterns is enhanced. This also reduces any issues with delamination. Also, the seed layer pattern prevents the metal that forms the rerouting pattern from being diffused to the organic insulation pattern. Therefore, a semiconductor device with enhanced reliability may be implemented.

Abstract translation: 在半导体器件中，有机绝缘图案设置在第一和第二重新布线图案之间。 有机绝缘图案可以吸收当第一和第二重新布线图案在加热下膨胀时发生的物理应力。 由于有机绝缘图案设置在第一和第二重新布线图案之间，所以可以相对于其中在重新布线图案之间设置半导体图案的半导体器件来增加绝缘性能。 此外，由于在第一和第二重新布线图案和有机绝缘图案之间以及基板和有机绝缘图案之间设置种子层图案，所以第一和第二布线图案的粘合强度提高。 这也减少了分层问题。 此外，种子层图案防止形成重新布线图案的金属扩散到有机绝缘图案。 因此，可以实现具有增强的可靠性的半导体器件。

公开(公告)号：US12237391B2

公开(公告)日：2025-02-25

申请号：US17851289

申请日：2022-06-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junggun You ,  Beomjin Park ,  Sughyun Sung ,  Hojin Lee ,  Dongwon Kim ,  Donggyu Lee ,  Myoung-Sun Lee ,  Keun Hwi Cho ,  Hanbyul Choi ,  Jiyong Ha

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device includes: an active pattern on a substrate, wherein the active pattern includes a plurality of channel layers stacked on one another; a plurality of source/drain patterns spaced apart from each other in a first direction and disposed on the active pattern, wherein the plurality of source/drain patterns are connected to each other through the plurality of channel layers; and first and second gate electrodes at least partially surrounding the channel layers and extending in a second direction, wherein the second direction intersects the first direction, wherein the active pattern has a first sidewall and a second sidewall that faces the first sidewall, and wherein a first distance between the first sidewall of the active pattern and an outer sidewall of the first gate electrode is different from a second distance between the second sidewall of the active pattern and an outer sidewall of the second gate electrode.

公开(公告)号：US20230352410A1

公开(公告)日：2023-11-02

申请号：US18347512

申请日：2023-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinnam Kim ,  Kwangjin Moon ,  Hojin Lee ,  Pilkyu Kang ,  Hoonjoo Na

IPC: H01L23/535 ,  H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L21/768 ,  H01L23/48 ,  H01L23/528 ,  H01L23/485

CPC classification number: H01L23/535 ,  H01L29/7851 ,  H01L29/0847 ,  H01L29/0653 ,  H01L29/41791 ,  H01L29/66795 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76895 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5286 ,  H01L23/485

Abstract: A semiconductor device includes a substrate having a first and second surface opposite to each other, and an active region on the first surface and defined by a first isolation region; a plurality of active fins on the active region, extending in a first direction, and defined by a second isolation region having a second depth smaller than a first depth of the first isolation region; a buried conductive wiring in a trench adjacent to the fins, and extending in a direction of the trench; a filling insulation portion in the trench, and having the wiring therein; an interlayer insulation layer on the first and second isolation regions and on the buried conductive wiring; a contact structure penetrating the interlayer insulation layer, and contacting the buried conductive wiring; and a conductive through structure extending through the substrate from the second surface to the trench, and contacting the buried conductive wiring.