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    SEMICONDUCTOR MEMORY DEVICE AND SYSTEM INCLUDING THE SAME
    2.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND SYSTEM INCLUDING THE SAME 有权

    公开(公告)号：US20220083260A1

    公开(公告)日：2022-03-17

    申请号：US17245325

    申请日：2021-04-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Haesuk LEE ,  Reum OH ,  Youngcheon KWON ,  Beomyong KIL ,  Jemin RYU ,  Jihyun CHOI

    IPC: G06F3/06

    Abstract: A semiconductor memory device includes an interface semiconductor die, at least one memory semiconductor die, and through-silicon vias connecting the interface semiconductor die and the memory semiconductor die. The interface semiconductor die includes command pins to receive command signals transferred from a memory controller and an interface command decoder to decode the command signals. The memory semiconductor die includes a memory integrated circuit configured to store data and a memory command decoder to decode the command signals transferred from the interface semiconductor die. The interface semiconductor die does not include a clock enable pin to receive a clock enable signal from the memory controller. The interface and memory command decoders generate interface and memory clock enable signals to control clock supply with respect to the interface and memory semiconductor dies based on a power mode command transferred through the plurality of command pins from the memory controller.

    MEMORY DEVICE SAMPLING DATA USING CONTROL SIGNAL TRANSMITTED THROUGH TSV
    3.
    发明申请
    MEMORY DEVICE SAMPLING DATA USING CONTROL SIGNAL TRANSMITTED THROUGH TSV 审中-公开

    公开(公告)号：US20190303042A1

    公开(公告)日：2019-10-03

    申请号：US16197877

    申请日：2018-11-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： So-young KIM ,  Reum OH ,  Haesuk LEE

    IPC: G06F3/06 ,  H01L25/18 ,  G11C11/4093 ,  G11C11/4076 ,  H01L23/48 ,  G11C11/408 ,  H01L25/065

    Abstract: A memory die of a memory device includes a first first-in first-out (FIFO) circuit that samples data output from a memory cell array and outputs the data to a buffer die through a first through silicon via, based on a control signal transmitted from the buffer die. A buffer die of the memory device includes a second FIFO circuit that samples the data output from the first FIFO unit based on the control signal transmitted from the memory die through a second through silicon via, a calibration circuit that generates a delay code, based on a latency of a path from the buffer die to the first FIFO circuit and from the first FIFO circuit to the second FIFO circuit, and a delay control circuit that generates the control signal transmitted to the memory die through a third through silicon via, based on the read command and the delay code.

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