公开(公告)号：US20230290818A1

公开(公告)日：2023-09-14

申请号：US18200638

申请日：2023-05-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seonbae KIM ,  Woojin LEE ,  Seunghoon CHOI

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/423 ,  H01L29/417

CPC classification number: H01L29/0649 ,  H01L29/785 ,  H01L29/42364 ,  H01L29/41791

Abstract: A semiconductor device includes active regions on a substrate, a gate structure intersecting the active regions, a source/drain region on the active regions and at a side surface of the gate structure, a gate spacer between the gate structure and the source/drain region, the gate spacer contacting the side surface of the gate structure, a lower source/drain contact plug connected to the source/drain region, a gate isolation layer on the gate spacer, an upper end of the gate isolation layer being at a higher level than an upper surface of the gate structure and an upper surface of the lower source/drain contact plug, a capping layer covering the gate structure, the lower source/drain contact plug, and the gate isolation layer, and an upper source/drain contact plug connected to the lower source/drain contact plug and extending through the capping layer.

公开(公告)号：US20230047343A1

公开(公告)日：2023-02-16

申请号：US17734473

申请日：2022-05-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Doohyun LEE ,  Heonjong SHIN ,  Minchan GWAK ,  Seonbae KIM ,  Jinyoung PARK ,  Hyunho PARK

IPC: H01L23/535 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/768 ,  H01L29/66

Abstract: A semiconductor device includes active regions extending in a first direction on a substrate; a gate electrode intersecting the active regions on the substrate, extending in a second direction, and including a contact region protruding upwardly; and an interconnection line on the gate electrode and connected to the contact region, wherein the contact region includes a lower region having a first width in the second direction and an upper region located on the lower region and having a second width smaller than the first width in the second direction, and wherein at least one side surface of the contact region in the second direction has a point at which an inclination or a curvature is changed between the lower region and the upper region.

公开(公告)号：US20230223451A1

公开(公告)日：2023-07-13

申请号：US18073682

申请日：2022-12-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Doohyun LEE ,  Heonjong SHIN ,  Seonbae KIM ,  Jinyoung PARK ,  Hyunho PARK ,  Jimin YU ,  Jaeran JANG

IPC: H01L29/417 ,  H01L23/528 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/41733 ,  H01L23/5286 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/401 ,  H01L29/66439

Abstract: A semiconductor device includes an active region extending in a first direction; a device isolation layer on side surfaces of the active region and defining the active region; a gate structure intersecting the active region on the active region and extending in a second direction; source/drain regions in regions in which the active region is recessed, on both sides of the gate structure; first protective layers between the device isolation layer and the gate structure; and a buried interconnection line below the source/drain regions and connected to one of the source/drain regions through an upper surface of the buried interconnection line.

公开(公告)号：US20220254880A1

公开(公告)日：2022-08-11

申请号：US17400358

申请日：2021-08-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seonbae KIM ,  Woojin LEE ,  Seunghoon CHOI

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78

Abstract: A semiconductor device includes active regions on a substrate, a gate structure intersecting the active regions, a source/drain region on the active regions and at a side surface of the gate structure, a gate spacer between the gate structure and the source/drain region, the gate spacer contacting the side surface of the gate structure, a lower source/drain contact plug connected to the source/drain region, a gate isolation layer on the gate spacer, an upper end of the gate isolation layer being at a higher level than an upper surface of the gate structure and an upper surface of the lower source/drain contact plug, a capping layer covering the gate structure, the lower source/drain contact plug, and the gate isolation layer, and an upper source/drain contact plug connected to the lower source/drain contact plug and extending through the capping layer.

公开(公告)号：US20230129825A1

公开(公告)日：2023-04-27

申请号：US17828327

申请日：2022-05-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeonggil KIM ,  Seonbae KIM ,  Woojin LEE ,  Jayeong HEO

IPC: H01L27/118

Abstract: An integrated circuit (IC) device including a fin-type active region on a substrate and a gate line on the fin-type active and having a first uppermost surface at a first vertical level, an insulating spacer covering a sidewall of the gate line and having a second uppermost surface at the first vertical level, and an insulating guide film covering the second uppermost surface of the insulating spacer may be provided. The gate line may include a multilayered conductive film structure that includes a plurality of conductive patterns and have a top surface defined by the conductive patterns, which includes at least first and second conductive patterns including different materials from each other and a unified conductive pattern that is in contact with a top surface of each of the conductive patterns and has a top surface that defines the first uppermost surface.

公开(公告)号：US20220406888A1

公开(公告)日：2022-12-22

申请号：US17574074

申请日：2022-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Doohyun LEE ,  Heonjong SHIN ,  Seonbae KIM ,  Sungmin KIM ,  Jinyoung PARK ,  Hyunho PARK

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor device is provided. The semiconductor device includes: an active pattern provided on a substrate having an upper surface; an insulation pattern provided above the substrate and contacting an upper surface of the active pattern; channels spaced apart from each other along a direction perpendicular to the upper surface of the substrate, each of the channels including a material provided in the active pattern; and a gate structure contacting an upper surface of the insulation pattern, an upper surface of the channels, a lower surface of the channels, and sidewalls of the channels opposite to each other. A first distance between an upper surface of the active pattern and a lowermost one of the channels is greater than a second distance between an upper surface of one of the channels and a lower surface of an adjacent channel.

公开(公告)号：US20250107150A1

公开(公告)日：2025-03-27

申请号：US18650292

申请日：2024-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daesik KIM ,  Seonbae KIM ,  Taeyong KWON ,  Changhee KIM ,  Doohyun LEE ,  Jaehyun KANG ,  Jinyoung PARK ,  Hyunho PARK ,  Jimin YU ,  Jinwook LEE ,  Seunghyun HWANG

IPC: H01L29/417 ,  H01L21/285 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/775

Abstract: A semiconductor device includes a substrate including an active region, a gate structure on the substrate, a plurality of channel layers on the active region, spaced apart from each other and surrounded by the gate structure, a source/drain region in a region at which the active region is recessed, on at least one side of the gate structure, and connected to the channel layers, and a contact plug partially recessing the source/drain region from an upper surface of the source/drain region, electrically connected to the source/drain region, and including a metal-semiconductor compound layer along a recessed surface of the source/drain region and a contact conductor layer on the metal-semiconductor compound layer, wherein the metal-semiconductor compound layer has a first thickness on a side surface of the contact conductive layer and a second thickness on a bottom surface of the contact plug, the second thickness being smaller than the first thickness.

公开(公告)号：US20240321980A1

公开(公告)日：2024-09-26

申请号：US18596772

申请日：2024-03-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Doohyun LEE ,  Heonjong SHIN ,  Jaehyun KANG ,  Seonbae KIM ,  Wangseop LIM ,  Seunghyun HWANG

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/41733 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: An integrated circuit device includes a substrate having a main surface and fin-type active regions protruding in a vertical direction from the main surface and extending lengthwise in a first horizontal direction, gate lines extending parallel to one another in a second horizontal direction perpendicular to the first horizontal direction and crossing the fin-type active regions, source/drain regions on the fin-type active regions between the gate lines, an inter-gate insulation layer covering the source/drain regions between the gate lines, active contacts on and in contact with the source/drain regions, and a buried insulation block between adjacent ones of the source/drain regions in the second horizontal direction, the buried insulation block penetrating through at least a portion of the inter-gate insulation layer and having a top surface in contact with a first active contact of the active contacts.

公开(公告)号：US20230231023A1

公开(公告)日：2023-07-20

申请号：US18085331

申请日：2022-12-20

Applicant: SAMSUNG ELECTRONICS CO, LTD.

Inventor： Doohyun LEE ,  Heonjong SHIN ,  Seonbae KIM ,  Jinyoung PARK ,  Hyunho PARK ,  Jimin YU ,  Jaeran JANG

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/41733 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/401 ,  H01L29/66439

Abstract: A semiconductor device includes a substrate, active regions extending in a first horizontal direction on the substrate, and including first and second active regions spaced apart from each other in a second horizontal direction perpendicular to the first horizontal direction, and third and fourth active regions spaced apart from each other in the second horizontal direction, first to fourth source/drain regions on the first to fourth active regions, first to fourth contact plugs connected to the first to fourth source/drain regions, a first isolation insulating pattern disposed between the first and second contact plugs, and a second isolation insulating pattern disposed between the third and fourth contact plugs, wherein a first length of the first isolation insulating pattern is smaller than a second length of the second isolation insulating pattern in a vertical direction.