公开(公告)号：US11848285B2

公开(公告)日：2023-12-19

申请号：US17671818

申请日：2022-02-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwangwuk Park ,  Youngmin Lee ,  Inyoung Lee ,  Sungdong Cho

IPC: H01L23/58 ,  H01L25/065 ,  H01L23/522

CPC classification number: H01L23/585 ,  H01L23/5226 ,  H01L25/0657

Abstract: A semiconductor chip, a semiconductor package including the same, and a method of fabricating the same, the semiconductor chip including a substrate that includes a device region and an edge region; a device layer and a wiring layer that are sequentially stacked on the substrate; a subsidiary pattern on the wiring layer on the edge region; a first capping layer that covers a sidewall of the subsidiary pattern, a top surface of the wiring layer, and a sidewall of the wiring layer, the first capping layer including an upper outer sidewall and a lower outer sidewall, the lower outer sidewall being offset from the upper outer sidewall; and a buried dielectric pattern in contact with the lower outer sidewall of the first capping layer and spaced apart from the upper outer sidewall of the first capping layer.

公开(公告)号：US11791242B2

公开(公告)日：2023-10-17

申请号：US17371602

申请日：2021-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwangwuk Park ,  Youngmin Lee ,  Hyoungyol Mun ,  Inyoung Lee ,  Seokhwan Jeong ,  Sungdong Cho

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/528 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/5283 ,  H01L23/5286 ,  H01L25/0657 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06586

Abstract: A semiconductor device, includes: a substrate having a first surface on which a plurality of devices are disposed and a second surface, opposite to the first surface; an interlayer insulating film on the first surface of the substrate; an etching delay layer disposed in a region between the substrate and the interlayer insulating film; first and second landing pads on the interlayer insulating film; a first through electrode penetrating through the substrate and the interlayer insulating film; and a second through electrode penetrating the substrate, the etching delay layer, and the interlayer insulating film, the second through electrode having a width, greater than that of the first through electrode, wherein each of the first and second through electrodes includes first and second tapered end portions in the interlayer insulating film, each of first and second tapered end portions having a cross-sectional shape narrowing closer to the landing pads.

公开(公告)号：US20250087531A1

公开(公告)日：2025-03-13

申请号：US18955826

申请日：2024-11-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangjun Park ,  Byungkyu Kim ,  Eunji Kim ,  Seungwoo Paek ,  Sungdong Cho

IPC: H01L21/768 ,  H01L23/00 ,  H01L23/522 ,  H01L25/065 ,  H01L25/18

Abstract: A semiconductor chip structure includes a first semiconductor chip that includes a first chip region and a first scribe lane region and a second semiconductor chip that includes a second chip region and a second scribe lane region respectively bonded to the first chip region and the first scribe lane region. The first semiconductor chip includes a first bonding wiring layer that includes a first bonding insulating layer and a first bonding electrode in the first bonding insulating layer. The second semiconductor chip includes a second bonding wiring layer that includes a second bonding insulating layer and a second bonding electrode in the second bonding insulating layer and a polishing stop pattern. The first bonding insulating layer and the first bonding electrode of the first bonding wiring layer are respectively hybrid bonded to the second bonding insulating layer and the second bonding electrode of the second bonding wiring layer.

公开(公告)号：US11990450B2

公开(公告)日：2024-05-21

申请号：US17315716

申请日：2021-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunji Kim ,  Seungwoo Paek ,  Byungkyu Kim ,  Sangjun Park ,  Sungdong Cho

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L23/538 ,  H01L29/423 ,  H10B43/40 ,  H10B43/27 ,  H10B43/35

CPC classification number: H01L25/0657 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/08 ,  H01L29/42344 ,  H10B43/40 ,  H01L2224/08146 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2924/1431 ,  H01L2924/1438 ,  H10B43/27 ,  H10B43/35

Abstract: A device including a first structure and a second structure is provided. The device includes a substrate, a peripheral circuit and first junction pads on the substrate; a first insulating structure surrounding side surfaces of the first junction pads; second junction pads contacting the first junction pads; a second insulating structure on the first insulating structure; a passivation layer on the second insulating structure; an upper insulating structure between the passivation layer and the second insulating structure; a barrier capping layer between the upper insulating structure and the passivation layer; conductive patterns spaced apart from each other in the upper insulating structure; a first pattern structure between the upper insulating structure and the second insulating structure; a stack structure between the second insulating structure and the first pattern structure, and including gate layers; and a vertical structure passing through the stack structure and including a data storage structure and a channel layer.

公开(公告)号：US12183680B2

公开(公告)日：2024-12-31

申请号：US18191418

申请日：2023-03-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyeok Son ,  Junwoo Lee ,  Sungdong Cho

IPC: H01L23/535 ,  H01L21/768 ,  H10B12/00

Abstract: A semiconductor memory device includes a substrate including a cell area and a peripheral area, a plurality of capacitors including a plurality of lower electrodes arranged in the cell area, a plurality of capacitor dielectric layers covering the plurality of lower electrodes, and an upper electrode on the plurality of capacitor dielectric layers, an etch stop layer covering the upper electrode, a filling insulation layer covering the etch stop layer and arranged in the cell area and the peripheral area, a plurality of wiring lines on the filling insulation layer, and a first wiring contact plug electrically connecting at least one of the plurality of wiring lines to the upper electrode. The upper electrode includes a first upper electrode layer covering the plurality of capacitor dielectric layers and including a semiconductor material and a second upper electrode layer covering the first upper electrode layer and including a metallic material.

公开(公告)号：US12176245B2

公开(公告)日：2024-12-24

申请号：US17453504

申请日：2021-11-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangjun Park ,  Byungkyu Kim ,  Eunji Kim ,  Seungwoo Paek ,  Sungdong Cho

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: A semiconductor chip structure includes a first semiconductor chip that includes a first chip region and a first scribe lane region and a second semiconductor chip that includes a second chip region and a second scribe lane region respectively bonded to the first chip region and the first scribe lane region. The first semiconductor chip includes a first bonding wiring layer that includes a first bonding insulating layer and a first bonding electrode in the first bonding insulating layer. The second semiconductor chip includes a second bonding wiring layer that includes a second bonding insulating layer and a second bonding electrode in the second bonding insulating layer and a polishing stop pattern. The first bonding insulating layer and the first bonding electrode of the first bonding wiring layer are respectively hybrid bonded to the second bonding insulating layer and the second bonding electrode of the second bonding wiring layer.

公开(公告)号：US20230238331A1

公开(公告)日：2023-07-27

申请号：US18191418

申请日：2023-03-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyeok Son ,  Junwoo Lee ,  Sungdong Cho

IPC: H01L23/535 ,  H01L21/768 ,  H10B12/00

CPC classification number: H01L23/535 ,  H01L21/76805 ,  H10B12/485 ,  H01L21/76843 ,  H10B12/34 ,  H10B12/315 ,  H10B12/50 ,  H10B12/482 ,  H01L21/76895 ,  H10B12/0335 ,  H10B12/09 ,  H10B12/053

Abstract: A semiconductor memory device includes a substrate including a cell area and a peripheral area, a plurality of capacitors including a plurality of lower electrodes arranged in the cell area, a plurality of capacitor dielectric layers covering the plurality of lower electrodes, and an upper electrode on the plurality of capacitor dielectric layers, an etch stop layer covering the upper electrode, a filling insulation layer covering the etch stop layer and arranged in the cell area and the peripheral area, a plurality of wiring lines on the filling insulation layer, and a first wiring contact plug electrically connecting at least one of the plurality of wiring lines to the upper electrode. The upper electrode includes a first upper electrode layer covering the plurality of capacitor dielectric layers and including a semiconductor material and a second upper electrode layer covering the first upper electrode layer and including a metallic material.

公开(公告)号：US11569171B2

公开(公告)日：2023-01-31

申请号：US17330795

申请日：2021-05-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyeok Son ,  Junwoo Lee ,  Sungdong Cho

IPC: H01L27/108 ,  H01L21/768 ,  H01L23/535

Abstract: A semiconductor memory device includes a substrate including a cell area and a peripheral area, a plurality of capacitors including a plurality of lower electrodes arranged in the cell area, a plurality of capacitor dielectric layers covering the plurality of lower electrodes, and an upper electrode on the plurality of capacitor dielectric layers, an etch stop layer covering the upper electrode, a filling insulation layer covering the etch stop layer and arranged in the cell area and the peripheral area, a plurality of wiring lines on the filling insulation layer, and a first wiring contact plug electrically connecting at least one of the plurality of wiring lines to the upper electrode. The upper electrode includes a first upper electrode layer covering the plurality of capacitor dielectric layers and including a semiconductor material and a second upper electrode layer covering the first upper electrode layer and including a metallic material.

公开(公告)号：US11901297B2

公开(公告)日：2024-02-13

申请号：US18153028

申请日：2023-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyeok Son ,  Junwoo Lee ,  Sungdong Cho

IPC: H01L23/535 ,  H01L21/768 ,  H10B12/00

CPC classification number: H01L23/535 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76895 ,  H10B12/0335 ,  H10B12/053 ,  H10B12/09 ,  H10B12/315 ,  H10B12/34 ,  H10B12/482 ,  H10B12/485 ,  H10B12/50

Abstract: A semiconductor memory device includes a substrate including a cell area and a peripheral area, a plurality of capacitors including a plurality of lower electrodes arranged in the cell area, a plurality of capacitor dielectric layers covering the plurality of lower electrodes, and an upper electrode on the plurality of capacitor dielectric layers, an etch stop layer covering the upper electrode, a filling insulation layer covering the etch stop layer and arranged in the cell area and the peripheral area, a plurality of wiring lines on the filling insulation layer, and a first wiring contact plug electrically connecting at least one of the plurality of wiring lines to the upper electrode. The upper electrode includes a first upper electrode layer covering the plurality of capacitor dielectric layers and including a semiconductor material and a second upper electrode layer covering the first upper electrode layer and including a metallic material.

公开(公告)号：US11798866B2

公开(公告)日：2023-10-24

申请号：US17808533

申请日：2022-06-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunji Kim ,  Sungdong Cho ,  Kwangwuk Park ,  Sangjun Park ,  Daesuk Lee ,  Hakseung Lee

IPC: H01L23/48 ,  H01L21/768 ,  H01L25/18 ,  H01L23/528 ,  H01L23/498 ,  H01L21/3065

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L25/18 ,  H01L21/3065

Abstract: A semiconductor device includes a semiconductor substrate having an active surface on which semiconductor elements are provided. An interlayer insulating film is provided on the semiconductor substrate. A first via structure passes through the semiconductor substrate. The first via structure has a first diameter. A second via structure passes through the semiconductor substrate. The second via structure has a second diameter that is greater than the first diameter. The first via structure has a step portion that is in contact with the interlayer insulating film.