公开(公告)号：US20210013324A1

公开(公告)日：2021-01-14

申请号：US17038004

申请日：2020-09-30

Applicant: Samsung Electronics Co., Ltd. ,  Research & Business Foundation Sungkyunkwan University

Inventor： Jin Bum KIM ,  MunHyeon KIM ,  Hyoung Sub KIM ,  Tae Jin PARK ,  Kwan Heum LEE ,  Chang Woo NOH ,  Maria TOLEDANO LU QUE ,  Hong Bae PARK ,  Si Hyung LEE ,  Sung Man WHANG

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor device includes a substrate, a gate electrode on the substrate, a gate spacer on a sidewall of the gate electrode, an active pattern penetrating the gate electrode and the gate spacer, and an epitaxial pattern contacting the active pattern and the gate spacer. The gate electrode extends in a first direction. The gate spacer includes a semiconductor material layer. The active pattern extends in a second direction crossing the first direction.

公开(公告)号：US20190198639A1

公开(公告)日：2019-06-27

申请号：US16037922

申请日：2018-07-17

Applicant: Samsung Electronics Co., Ltd. ,  Research & Business Foundation Sungkyunkwan University

Inventor： Jin Bum KIM ,  MunHyeon KIM ,  Hyoung Sub KIM ,  Tae Jin PARK ,  Kwan Heum LEE ,  Chang Woo NOH ,  Maria TOLEDANO LU QUE ,  Hong Bae PARK ,  Si Hyung LEE ,  Sung Man WHANG

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/66545 ,  H01L29/42392 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/78696

Abstract: A semiconductor device includes a substrate, a gate electrode on the substrate, a gate spacer on a sidewall of the gate electrode, an active pattern penetrating the gate electrode and the gate spacer, and an epitaxial pattern contacting the active pattern and the gate spacer. The gate electrode extends in a first direction. The gate spacer includes a semiconductor material layer. The active pattern extends in a second direction crossing the first direction.

公开(公告)号：US20180130886A1

公开(公告)日：2018-05-10

申请号：US15685255

申请日：2017-08-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin Bum KIM ,  Gyeom KIM ,  Seok Hoon KIM ,  Tae Jin PARK ,  Jeong Ho YOO ,  Cho Eun LEE ,  Hyun Jung LEE ,  Sun Jung KIM ,  Dong Suk SHIN

IPC: H01L29/417 ,  H01L27/092 ,  H01L29/51 ,  H01L29/423 ,  H01L21/02 ,  H01L21/3205

CPC classification number: H01L29/41725 ,  H01L21/02425 ,  H01L21/32053 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/42356 ,  H01L29/517 ,  H01L2924/0002

Abstract: A semiconductor device includes: a substrate having an active region; a gate structure disposed in the active region; source/drain regions respectively formed within portions of the active region disposed on both sides of the gate structure; a metal silicide layer disposed on a surface of each of the source/drain regions; and contact plugs disposed on the source/drain regions and electrically connected to the source/drain regions through the metal silicide layer, respectively. The metal silicide layer is formed so as to have a monocrystalline structure.

公开(公告)号：US20240357795A1

公开(公告)日：2024-10-24

申请号：US18513011

申请日：2023-11-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae Jin PARK ,  Hui-Jung KIM ,  Sang Jae PARK ,  Ki Seok LEE ,  Myeong-Dong LEE

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/0335

Abstract: There is provided a semiconductor memory device comprising: a substrate; a base insulating film on an upper surface of the substrate; a plurality of first conductive patterns on the base insulating film and spaced apart from each other, wherein the plurality of first conductive patterns extend in a first direction; a spacer structure on a side surface of each of the plurality of first conductive patterns; a barrier metal film on a side surface of the spacer structure, wherein the barrier metal film extends through the base insulating film to be electrically connected to the substrate; a filling metal film on the barrier metal film, wherein the filling metal film fills at least a portion of a space between adjacent ones of the plurality of first conductive patterns; and a capacitor structure on the filling metal film, wherein the capacitor structure is electrically connected to the filling metal film.

公开(公告)号：US20230043936A1

公开(公告)日：2023-02-09

申请号：US17735292

申请日：2022-05-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae Jin PARK ,  Gyul GO ,  Jun Soo KIM ,  Gyung Hyun YOON ,  Eui Jun CHA ,  Hui-Jung KIM ,  Yoo Sang HWANG

IPC: H01L27/108

Abstract: A semiconductor device and a method for fabricating the same is provided. The semiconductor device includes a lower semiconductor film, a buried insulating film, and an upper semiconductor film which are sequentially stacked; an element isolation film defining an active region inside the substrate and including a material having an etching selectivity with respect to silicon oxide; a first gate trench inside the upper semiconductor film; a first gate electrode filing a part of the first gate trench; a second gate trench inside the element isolation film; and a second gate electrode filling a part of the second gate trench, a bottom side of the element isolation film being inside the lower semiconductor film.

公开(公告)号：US20210035613A1

公开(公告)日：2021-02-04

申请号：US16841850

申请日：2020-04-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae Jin PARK ,  Won Seok Yoo ,  Keun Nam Kim ,  Hyo-Sub Kim ,  So Hyun Park ,  In Kyoung Heo ,  Yoo Sang Hwang

IPC: G11C5/06 ,  H01L27/108

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate a bit line structure disposed on the substrate, a trench adjacent to at least one side of the bit line structure, a storage contact structure disposed within the trench, and comprising a storage contact, a silicide layer, and a storage pad which are stacked sequentially. A spacer structure is disposed between the bit line structure and the storage contact structure.

公开(公告)号：US20190267494A1

公开(公告)日：2019-08-29

申请号：US16254842

申请日：2019-01-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin Bum KIM ,  Hyoung Sub KIM ,  Seong Heum CHOI ,  Jin Yong KIM ,  Tae Jin PARK ,  Seung Hun LEE

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L21/30 ,  H01L29/66

Abstract: A semiconductor device includes a gate electrode extending in a first direction on a substrate, a first active pattern extending in a second direction intersecting the first direction on the substrate to penetrate the gate electrode, the first active pattern including germanium, an epitaxial pattern on a side wall of the gate electrode, a first semiconductor oxide layer between the first active pattern and the gate electrode, and including a first semiconductor material, and a second semiconductor oxide layer between the gate electrode and the epitaxial pattern, and including a second semiconductor material. A concentration of germanium of the first semiconductor material may be less than a concentration of germanium of the first active pattern, and the concentration of germanium of the first semiconductor material may be different from a concentration of germanium of the second semiconductor material.

公开(公告)号：US20190058051A1

公开(公告)日：2019-02-21

申请号：US15896277

申请日：2018-02-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin Bum KIM ,  Tae Jin PARK ,  Jong Min LEE ,  Seok Hoon KIM ,  Dong Chan SUH ,  Jeong Ho YOO ,  Ha Kyu SEONG ,  Dong Suk SHIN

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/40

Abstract: A semiconductor device and a method of manufacturing a semiconductor device, the semiconductor device including a channel pattern on a substrate, the channel pattern extending in a first direction; a gate pattern on the substrate, the gate pattern extending in a second direction crossing the first direction and surrounding the channel pattern; and an interface layer between the channel pattern and the gate pattern, the interface layer being formed on at least one surface of an upper surface and a lower surface of the channel pattern.

公开(公告)号：US20240357802A1

公开(公告)日：2024-10-24

申请号：US18525235

申请日：2023-11-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae Jin PARK ,  Hui Jung KIM

IPC: H10B12/00

CPC classification number: H10B12/485 ,  H10B12/053 ,  H10B12/315 ,  H10B12/34

Abstract: A semiconductor memory device comprising: a substrate including active patterns; a gate structure intersecting the active patterns; bit-line structures on the substrate; first contacts, wherein the bit-line structures and the first contacts are alternately arranged with each other; insulating patterns respectively disposed on the bit-line structures, wherein an insulating pattern among the insulating patterns is disposed in a first trench exposing a sidewall of a first contact among the first contacts and at least a portion of the gate structure; and second contacts disposed on the first contacts, wherein a second contact among the second contacts is disposed in a second trench exposing a sidewall of the insulating pattern and an upper surface of the first contact, wherein the insulating pattern overlaps an upper surface of a bit-line structure among the bit-line structures and extends along sidewalls of the first and second trenches and contacts the first and second contacts.