公开(公告)号：US20190067484A1

公开(公告)日：2019-02-28

申请号：US15995414

申请日：2018-06-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seok Hoon KIM ,  Dong Myoung KIM ,  Dong Suk SHIN ,  Seung Hun LEE ,  Cho Eun LEE ,  Hyun Jung LEE ,  Sung Uk JANG ,  Edward Nam Kyu CHO ,  Min-Hee CHOI

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/02

Abstract: A semiconductor device includes a first fin type pattern on a substrate, a second fin type pattern, parallel to the first fin type pattern, on the substrate, and an epitaxial pattern on the first and second fin type patterns. The epitaxial pattern may include a shared semiconductor pattern on the first fin type pattern and the second fin type pattern. The shared semiconductor pattern may include a first sidewall adjacent to the first fin type pattern and a second sidewall adjacent to the second fin type pattern. The first sidewall may include a first lower facet, a first upper facet on the first lower facet and a first connecting curved surface connecting the first lower and upper facets. The second sidewall may include a second lower facet, a second upper facet on the second lower facet and a second connecting curved surface connecting the second lower and upper facets.

公开(公告)号：US20180130886A1

公开(公告)日：2018-05-10

申请号：US15685255

申请日：2017-08-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin Bum KIM ,  Gyeom KIM ,  Seok Hoon KIM ,  Tae Jin PARK ,  Jeong Ho YOO ,  Cho Eun LEE ,  Hyun Jung LEE ,  Sun Jung KIM ,  Dong Suk SHIN

IPC: H01L29/417 ,  H01L27/092 ,  H01L29/51 ,  H01L29/423 ,  H01L21/02 ,  H01L21/3205

CPC classification number: H01L29/41725 ,  H01L21/02425 ,  H01L21/32053 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/42356 ,  H01L29/517 ,  H01L2924/0002

Abstract: A semiconductor device includes: a substrate having an active region; a gate structure disposed in the active region; source/drain regions respectively formed within portions of the active region disposed on both sides of the gate structure; a metal silicide layer disposed on a surface of each of the source/drain regions; and contact plugs disposed on the source/drain regions and electrically connected to the source/drain regions through the metal silicide layer, respectively. The metal silicide layer is formed so as to have a monocrystalline structure.

公开(公告)号：US20230037672A1

公开(公告)日：2023-02-09

申请号：US17692369

申请日：2022-03-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki Hwan KIM ,  Jeong Ho YOO ,  Cho Eun LEE ,  Yong Uk JEON ,  Young Dae CHO

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/417

Abstract: A semiconductor includes an active pattern with a lower pattern and sheet patterns spaced apart from the lower pattern in a first direction, a source/drain pattern on the lower pattern, the source/drain pattern being in contact with the sheet patterns, and gate structures on opposite sides of the source/drain pattern, the gate structures being spaced apart from each other along a second direction and including gate electrodes that surround the sheet patterns, wherein the source/drain pattern includes a first epitaxial region having at least one of antimony and bismuth, the first epitaxial region having a bottom part in contact with the lower pattern, but not with the sheet patterns, and a thickness of the bottom part increasing and decreasing away from the gate structures in the second direction, and a second epitaxial region on the first epitaxial region, the second epitaxial region including phosphorus.

公开(公告)号：US20170352759A1

公开(公告)日：2017-12-07

申请号：US15685459

申请日：2017-08-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nam Kyu KIM ,  Dong Chan SUH ,  Kwan Heum LEE ,  Byeong Chan LEE ,  Cho Eun LEE ,  Su Jin JUNG ,  Gyeom KIM ,  Ji Eon YOON

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/417 ,  H01L29/08

CPC classification number: H01L29/7848 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/7834

Abstract: A semiconductor device may include: a semiconductor substrate, a device isolating layer embedded within the semiconductor substrate and defining an active region, a channel region formed in the active region, a gate electrode disposed above the channel region, a gate insulating layer provided between the channel region and the gate electrode, and a silicon germanium epitaxial layer adjacent to the channel region within the active region and including a first epitaxial layer containing a first concentration of germanium, a second epitaxial layer containing a second concentration of germanium, higher than the first concentration, and a third epitaxial layer containing a third concentration of germanium, lower than the second concentration, the first to third epitaxial layers being sequentially stacked on one another in that order.

公开(公告)号：US20230387206A1

公开(公告)日：2023-11-30

申请号：US18117262

申请日：2023-03-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Hwan KIM ,  Kyung Ho KIM ,  Kang Hun MOON ,  Cho Eun LEE ,  Yong Uk JEON

IPC: H01L29/08 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/775 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4991 ,  H01L29/775 ,  H01L29/66545 ,  H01L29/66439

Abstract: A semiconductor device comprises an active pattern including a lower pattern and a plurality of sheet patterns that are spaced apart from the lower pattern in a first direction, a plurality of gate structures disposed on the lower pattern to be spaced apart from each other in a second direction, each of the gate structures including a gate electrode and gate insulating films, source/drain recesses defined between adjacent gate structures and a source/drain pattern filling the source/drain recesses. Each source/drain pattern may include a first semiconductor liner, which extend along sidewalls and a bottom surface of the source/drain recesses, second semiconductor liners, which are on the first semiconductor liners and extend along the sidewalls and the bottom surface of the source/drain recesses, and a filling semiconductor film, which is on the second semiconductor liners and fills the source/drain recess. The second semiconductor liners may be doped with carbon, and the first semiconductor liners may be in contact with the lower pattern and the sheet patterns, while the first semiconductor liners may include carbon-undoped regions.

公开(公告)号：US20180138269A1

公开(公告)日：2018-05-17

申请号：US15715832

申请日：2017-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok Hoon KIM ,  Hyun Jung LEE ,  Kyung Hee KIM ,  Sun Jung KIM ,  Jin Bum KIM ,  Il Gyou SHIN ,  Seung Hun LEE ,  Cho Eun LEE ,  Dong Suk SHIN

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/161 ,  H01L29/167 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L21/0257 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: There is provided a semiconductor device capable of enhancing short channel effect by forming a carbon-containing semiconductor pattern in a source/drain region. The semiconductor device includes a first gate electrode and a second gate electrode spaced apart from each other on a fin-type pattern, a recess formed in the fin-type pattern between the first gate electrode and the second gate electrode, and a semiconductor pattern including a lower semiconductor film formed along a profile of the recess and an upper semiconductor film on the lower semiconductor film, wherein the lower semiconductor film includes a lower epitaxial layer and an upper epitaxial layer sequentially formed on the fin-type pattern, and a carbon concentration of the upper epitaxial layer is greater than a carbon concentration of the lower epitaxial layer.

公开(公告)号：US20180096845A1

公开(公告)日：2018-04-05

申请号：US15595945

申请日：2017-05-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Cho Eun LEE ,  Jin Bum KIM ,  Kang Hun MOON ,  Jae Myung CHOE ,  Sun Jung KIM ,  Dong Suk SHIN ,  IL GYOU SHIN ,  Jeong Ho YOO

IPC: H01L21/02 ,  H01L21/223 ,  H01L29/66

CPC classification number: H01L21/02661 ,  H01L21/02071 ,  H01L21/223 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795

Abstract: A method of fabricating a semiconductor device is provided. The method includes forming a dummy gate electrode on a substrate, forming a trench on a side surface of the dummy gate electrode, performing a bake process of removing an impurity from the trench and forming a source/drain in the trench, wherein the bake process comprises a first stage and a second stage following the first stage, an air pressure in which the substrate is disposed during the first stage is different from an air pressure in which the substrate is disposed during the second stage, and the bake process is performed while the substrate is on a stage rotating the substrate, wherein a revolution per minute (RPM) of the substrate during the first stage is different from a revolution per minute (RPM) of the substrate during the second stage.