公开(公告)号：US20180138269A1

公开(公告)日：2018-05-17

申请号：US15715832

申请日：2017-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok Hoon KIM ,  Hyun Jung LEE ,  Kyung Hee KIM ,  Sun Jung KIM ,  Jin Bum KIM ,  Il Gyou SHIN ,  Seung Hun LEE ,  Cho Eun LEE ,  Dong Suk SHIN

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/161 ,  H01L29/167 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L21/0257 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: There is provided a semiconductor device capable of enhancing short channel effect by forming a carbon-containing semiconductor pattern in a source/drain region. The semiconductor device includes a first gate electrode and a second gate electrode spaced apart from each other on a fin-type pattern, a recess formed in the fin-type pattern between the first gate electrode and the second gate electrode, and a semiconductor pattern including a lower semiconductor film formed along a profile of the recess and an upper semiconductor film on the lower semiconductor film, wherein the lower semiconductor film includes a lower epitaxial layer and an upper epitaxial layer sequentially formed on the fin-type pattern, and a carbon concentration of the upper epitaxial layer is greater than a carbon concentration of the lower epitaxial layer.

公开(公告)号：US20200241423A1

公开(公告)日：2020-07-30

申请号：US16577372

申请日：2019-09-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun Jung LEE ,  Ji Hun CHEON ,  Won Jun LEE

IPC: G03F7/42 ,  H01L21/67

Abstract: An apparatus for removing photoresists includes a chamber including a substrate support, configured to support a substrate, and a nozzle unit disposed toward the substrate support, an ozone solution generator configured to generate an ozone solution, an acid solution reservoir configured to store an acid solution, first and second supply lines connected to the ozone solution generator and the acid solution reservoir respectively, and an in-line mixer configured to prepare a photoresist removing solution by mixing the ozone solution supplied from the first supply line, and the acid solution supplied from the second supply line, and supply the photoresist removing solution to the nozzle unit.

公开(公告)号：US20170092547A1

公开(公告)日：2017-03-30

申请号：US15234170

申请日：2016-08-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Poren Tang ,  Sunjung Steve KIM ,  Moon Seung YANG ,  Seung Hun LEE ,  Hyun Jung LEE ,  Geun Hee JEONG

IPC: H01L21/8238 ,  H01L21/306 ,  H01L21/308 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L29/10 ,  H01L21/02 ,  H01L27/092

CPC classification number: H01L21/823892 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02458 ,  H01L21/02463 ,  H01L21/02499 ,  H01L21/02532 ,  H01L21/0254 ,  H01L21/02546 ,  H01L21/30604 ,  H01L21/30612 ,  H01L21/308 ,  H01L21/823807 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/78

Abstract: Methods of fabricating semiconductor device are provided including forming first and second material layers for a first transistor using epitaxial growth processes. A recess region is formed by partially etching the first and second material layers. Third and fourth material layers for a second transistor are formed using epitaxial growth processes.

公开(公告)号：US20180130886A1

公开(公告)日：2018-05-10

申请号：US15685255

申请日：2017-08-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin Bum KIM ,  Gyeom KIM ,  Seok Hoon KIM ,  Tae Jin PARK ,  Jeong Ho YOO ,  Cho Eun LEE ,  Hyun Jung LEE ,  Sun Jung KIM ,  Dong Suk SHIN

IPC: H01L29/417 ,  H01L27/092 ,  H01L29/51 ,  H01L29/423 ,  H01L21/02 ,  H01L21/3205

CPC classification number: H01L29/41725 ,  H01L21/02425 ,  H01L21/32053 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/42356 ,  H01L29/517 ,  H01L2924/0002

Abstract: A semiconductor device includes: a substrate having an active region; a gate structure disposed in the active region; source/drain regions respectively formed within portions of the active region disposed on both sides of the gate structure; a metal silicide layer disposed on a surface of each of the source/drain regions; and contact plugs disposed on the source/drain regions and electrically connected to the source/drain regions through the metal silicide layer, respectively. The metal silicide layer is formed so as to have a monocrystalline structure.

公开(公告)号：US20170195772A1

公开(公告)日：2017-07-06

申请号：US15399140

申请日：2017-01-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Woo HAN ,  Ji Ho LEE ,  Hyun Jung LEE

IPC: H04R1/10 ,  A61B5/00 ,  A61B5/024 ,  G06F3/0481 ,  G06F3/0488

CPC classification number: H04R1/1041 ,  A61B5/02438 ,  A61B5/6803 ,  A61B5/6817 ,  A61B5/6844 ,  G06F3/011 ,  G06F3/0481 ,  G06F3/0488 ,  H04R1/1016 ,  H04R2420/07

Abstract: Systems, methods, and audio output devices are described. In one aspect, an audio output device includes a communication module that communicates with an external electronic device, a speaker that outputs sound, a mounting detection sensor that detects whether the audio output device is mounted on a user of the audio output device, and a control circuit that is electrically connected with the communication module, the speaker, and the mounting detection sensor. The control circuit wirelessly connects the external electronic device with the audio output device using the communication module if the mounting of the audio output device is detected by the mounting detection sensor, receives audio data from the external electronic device through the wireless connection, and outputs the audio data using the speaker.

公开(公告)号：US20220262814A1

公开(公告)日：2022-08-18

申请号：US17738516

申请日：2022-05-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Hoon SON ,  Hyung Joon KIM ,  Hyun Jung LEE

IPC: H01L27/11565 ,  H01L27/108

Abstract: Disclosed are semiconductor memory devices and methods of fabricating the same. The semiconductor memory device comprises a first semiconductor pattern that is on a substrate and that includes a first end and a second end that face each other, a first conductive line that is adjacent to a lateral surface of the first semiconductor pattern between the first and second ends and that is perpendicular to a top surface of the substrate, a second conductive line that is in contact with the first end of the first semiconductor pattern, is spaced part from the first conductive line, and is parallel to the top surface of the substrate, and a data storage pattern in contact with the second end of the first semiconductor pattern. The first conductive line has a protrusion that protrudes adjacent to the lateral surface of the first semiconductor pattern.

公开(公告)号：US20190067484A1

公开(公告)日：2019-02-28

申请号：US15995414

申请日：2018-06-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seok Hoon KIM ,  Dong Myoung KIM ,  Dong Suk SHIN ,  Seung Hun LEE ,  Cho Eun LEE ,  Hyun Jung LEE ,  Sung Uk JANG ,  Edward Nam Kyu CHO ,  Min-Hee CHOI

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/02

Abstract: A semiconductor device includes a first fin type pattern on a substrate, a second fin type pattern, parallel to the first fin type pattern, on the substrate, and an epitaxial pattern on the first and second fin type patterns. The epitaxial pattern may include a shared semiconductor pattern on the first fin type pattern and the second fin type pattern. The shared semiconductor pattern may include a first sidewall adjacent to the first fin type pattern and a second sidewall adjacent to the second fin type pattern. The first sidewall may include a first lower facet, a first upper facet on the first lower facet and a first connecting curved surface connecting the first lower and upper facets. The second sidewall may include a second lower facet, a second upper facet on the second lower facet and a second connecting curved surface connecting the second lower and upper facets.

公开(公告)号：US20160056269A1

公开(公告)日：2016-02-25

申请号：US14749037

申请日：2015-06-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun Jung LEE ,  Bonyoung KOO ,  Sunjung KIM ,  Jongryeol YOO ,  Seung Hun LEE ,  Poren TANG

IPC: H01L29/66 ,  H01L21/762 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308

CPC classification number: H01L29/66795 ,  H01L21/3085 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823807

Abstract: A method of fabricating a semiconductor device includes forming a channel layer on a substrate, forming a sacrificial layer on the channel layer, forming a hardmask pattern on the sacrificial layer, and performing a patterning process using the hardmask pattern as an etch mask to form a channel portion with an exposed top surface. The channel and sacrificial layers may be formed of silicon germanium, and the sacrificial layer may have a germanium content higher than that of the channel layer.

Abstract translation: 制造半导体器件的方法包括在衬底上形成沟道层，在沟道层上形成牺牲层，在牺牲层上形成硬掩模图案，并使用硬掩模图案作为蚀刻掩模进行图案化处理，形成 通道部分具有​​暴露的顶表面。 通道和牺牲层可由硅锗形成，并且牺牲层的锗含量可高于沟道层的锗含量。