公开(公告)号：US20180096845A1

公开(公告)日：2018-04-05

申请号：US15595945

申请日：2017-05-16

申请人： Samsung Electronics Co., Ltd.

发明人： Cho Eun LEE ,  Jin Bum KIM ,  Kang Hun MOON ,  Jae Myung CHOE ,  Sun Jung KIM ,  Dong Suk SHIN ,  IL GYOU SHIN ,  Jeong Ho YOO

IPC分类号： H01L21/02 ,  H01L21/223 ,  H01L29/66

CPC分类号： H01L21/02661 ,  H01L21/02071 ,  H01L21/223 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795

摘要： A method of fabricating a semiconductor device is provided. The method includes forming a dummy gate electrode on a substrate, forming a trench on a side surface of the dummy gate electrode, performing a bake process of removing an impurity from the trench and forming a source/drain in the trench, wherein the bake process comprises a first stage and a second stage following the first stage, an air pressure in which the substrate is disposed during the first stage is different from an air pressure in which the substrate is disposed during the second stage, and the bake process is performed while the substrate is on a stage rotating the substrate, wherein a revolution per minute (RPM) of the substrate during the first stage is different from a revolution per minute (RPM) of the substrate during the second stage.

公开(公告)号：US20180130886A1

公开(公告)日：2018-05-10

申请号：US15685255

申请日：2017-08-24

申请人： Samsung Electronics Co., Ltd.

发明人： Jin Bum KIM ,  Gyeom KIM ,  Seok Hoon KIM ,  Tae Jin PARK ,  Jeong Ho YOO ,  Cho Eun LEE ,  Hyun Jung LEE ,  Sun Jung KIM ,  Dong Suk SHIN

IPC分类号： H01L29/417 ,  H01L27/092 ,  H01L29/51 ,  H01L29/423 ,  H01L21/02 ,  H01L21/3205

CPC分类号： H01L29/41725 ,  H01L21/02425 ,  H01L21/32053 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/42356 ,  H01L29/517 ,  H01L2924/0002

摘要： A semiconductor device includes: a substrate having an active region; a gate structure disposed in the active region; source/drain regions respectively formed within portions of the active region disposed on both sides of the gate structure; a metal silicide layer disposed on a surface of each of the source/drain regions; and contact plugs disposed on the source/drain regions and electrically connected to the source/drain regions through the metal silicide layer, respectively. The metal silicide layer is formed so as to have a monocrystalline structure.

公开(公告)号：US20190296144A1

公开(公告)日：2019-09-26

申请号：US16162510

申请日：2018-10-17

申请人： Samsung Electronics Co., Ltd.

发明人： Su Jin JUNG ,  Jeong Ho YOO ,  Jong Ryeol YOO ,  Young Dae CHO

IPC分类号： H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L29/06 ,  H01L21/768 ,  H01L21/308 ,  H01L29/36

摘要： A semiconductor device and a method of manufacturing a semiconductor device, the device including an active pattern protruding from a substrate; a plurality of gate structures each including a gate electrode and crossing the active pattern; and a source/drain region between the plurality of gate structures, wherein the source/drain region includes a high concentration doped layer in contact with a bottom surface of a recessed region in the active pattern, a first epitaxial layer in contact with an upper surface of the high concentration doped layer and a sidewall of the recessed region, and a second epitaxial layer on the first epitaxial layer, and the high concentration doped layer has a first area in contact with the bottom surface of the recessed region and a second area in contact with the sidewall of the recessed region, the first area being wider than the second area.

公开(公告)号：US20230037672A1

公开(公告)日：2023-02-09

申请号：US17692369

申请日：2022-03-11

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Ki Hwan KIM ,  Jeong Ho YOO ,  Cho Eun LEE ,  Yong Uk JEON ,  Young Dae CHO

IPC分类号： H01L29/786 ,  H01L29/66 ,  H01L29/417

摘要： A semiconductor includes an active pattern with a lower pattern and sheet patterns spaced apart from the lower pattern in a first direction, a source/drain pattern on the lower pattern, the source/drain pattern being in contact with the sheet patterns, and gate structures on opposite sides of the source/drain pattern, the gate structures being spaced apart from each other along a second direction and including gate electrodes that surround the sheet patterns, wherein the source/drain pattern includes a first epitaxial region having at least one of antimony and bismuth, the first epitaxial region having a bottom part in contact with the lower pattern, but not with the sheet patterns, and a thickness of the bottom part increasing and decreasing away from the gate structures in the second direction, and a second epitaxial region on the first epitaxial region, the second epitaxial region including phosphorus.

公开(公告)号：US20190058051A1

公开(公告)日：2019-02-21

申请号：US15896277

申请日：2018-02-14

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jin Bum KIM ,  Tae Jin PARK ,  Jong Min LEE ,  Seok Hoon KIM ,  Dong Chan SUH ,  Jeong Ho YOO ,  Ha Kyu SEONG ,  Dong Suk SHIN

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/40

摘要： A semiconductor device and a method of manufacturing a semiconductor device, the semiconductor device including a channel pattern on a substrate, the channel pattern extending in a first direction; a gate pattern on the substrate, the gate pattern extending in a second direction crossing the first direction and surrounding the channel pattern; and an interface layer between the channel pattern and the gate pattern, the interface layer being formed on at least one surface of an upper surface and a lower surface of the channel pattern.