公开(公告)号：US11023396B2

公开(公告)日：2021-06-01

申请号：US16519487

申请日：2019-07-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungup Moon ,  Tae-Kyeong Ko ,  Do-Han Kim ,  Jongmin Park ,  Kyoyeon Won

IPC: G06F13/16 ,  G06F12/0804 ,  G06F13/40 ,  G06F12/0868

Abstract: A memory system includes a nonvolatile memory electrically connected to a data bus, a DRAM electrically connected to the data bus, and a memory controller configured to drive the DRAM as a cache memory and the nonvolatile memory as a main memory and to synchronize data of a cache line with data of the nonvolatile memory in units of cache units based on a dirty flag. The DRAM is configured to load data of the cache line that caches data stored in the nonvolatile memory and to store the dirty flag, which indicates whether a cache unit is dirty, in units of cache units, where a size of each cache unit is smaller than a size of the cache line.

公开(公告)号：US11521374B2

公开(公告)日：2022-12-06

申请号：US17188166

申请日：2021-03-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chol-Min Kim ,  Tae-Kyeong Ko ,  Ji-Yong Lee ,  Deok-Ho Seo

IPC: G06V10/94 ,  G06K9/62 ,  G06T1/20 ,  G06N3/08 ,  G06T1/60

Abstract: An electronic device includes a graphic processor and a memory device. The graphic processor includes an artificial neural network engine that makes an object recognition model learn by using learning data and weights to provide a learned object recognition model. The memory device divides a feature vector into a first sub feature vector and a second feature vector, and performs a first calculation to apply the second sub feature vector and the weights to the learned object recognition model to provide a second object recognition result. The artificial neural network engine performs a second calculation to apply the first sub feature vector and the weights to the learned object recognition model to provide a first object recognition result and provides the first object recognition result to the memory device. The second calculation is performed in parallel with the first calculation.

公开(公告)号：US10936891B2

公开(公告)日：2021-03-02

申请号：US16295526

申请日：2019-03-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chol-Min Kim ,  Tae-Kyeong Ko ,  Ji-Yong Lee ,  Deok-Ho Seo

IPC: G06K9/00 ,  G06K9/62 ,  G06T1/20 ,  G06N3/08 ,  G06T1/60

Abstract: An electronic device includes a graphic processor and a memory device. The graphic processor includes an artificial neural network engine that makes an object recognition model learn by using learning data and weights to provide a learned object recognition model. The memory device, divides a feature vector into a first sub feature vector and a second feature vector, and performs a first calculation to apply the second sub feature vector and the weights to the learned object recognition model to provide a second object recognition result. The artificial neural network engine performs a second calculation to apply the first sub feature vector and the weights to the learned object recognition model to provide a first object recognition result and provides the first object recognition result to the memory device. The second calculation is performed in parallel with the first calculation.

公开(公告)号：US12236104B2

公开(公告)日：2025-02-25

申请号：US17889117

申请日：2022-08-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-Jeong Kim ,  Tae-Kyeong Ko ,  Nam Hyung Kim ,  Do-Han Kim ,  Deokho Seo ,  Ho-Young Lee ,  Insu Choi

IPC: G06F11/00 ,  G06F3/06 ,  G06F11/07

Abstract: An operation method of a memory controller, which is configured to control a memory module including a plurality of memory devices and at least one error correction code (ECC) device, is provided. The method includes reading a data set including user data stored in the plurality of memory devices and ECC data stored in the at least one ECC device, based on a read command and a first address, and writing uncorrectable data in a memory area, which is included in each of the plurality of memory devices and the at least one ECC device and corresponds to the first address, when an error of the user data is not corrected based on the ECC data.

公开(公告)号：US11157342B2

公开(公告)日：2021-10-26

申请号：US16164103

申请日：2018-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonjae Shin ,  Tae-Kyeong Ko ,  Dae-Jeong Kim ,  Sung-Joon Kim ,  Wooseop Kim ,  Chanik Park ,  Yongjun Yu ,  Insu Choi ,  Hui-Chung Byun ,  JongYoung Lee

IPC: G06F11/07

Abstract: A memory system includes a processor that includes cores and a memory controller, and a first semiconductor memory module that communicates with the memory controller. The cores receive a call to perform a first exception handling in response to detection of a first error when the memory controller reads first data from the first semiconductor memory module. A first monarchy core of the cores performs the first exception handling and the remaining cores of the cores return to remaining operations previously performed.

公开(公告)号：US09934830B2

公开(公告)日：2018-04-03

申请号：US15298335

申请日：2016-10-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongmin Park ,  Tae-Kyeong Ko ,  Do-Han Kim ,  Sungup Moon ,  Kyoyeon Won

IPC: G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C7/02

CPC classification number: G11C7/1012 ,  G11C7/02 ,  G11C7/22

Abstract: In a memory module including a memory device and a filter, the memory device operates with a clock of a reference frequency. The filter receives a multiplexed signal from a host and filters a signal of a frequency band from the multiplexed signal. The frequency band includes the reference frequency and the signal of the frequency band is provided to the memory device.

公开(公告)号：US20240339145A1

公开(公告)日：2024-10-10

申请号：US18422770

申请日：2024-01-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongha Kim ,  Tae-Kyeong Ko ,  Do-Han Kim

IPC: G11C11/406 ,  G11C11/4078

CPC classification number: G11C11/40615 ,  G11C11/40622 ,  G11C11/4078

Abstract: The present disclosure relates to operation methods of a memory device including multiple rows each including multiple memory cells. One example method includes receiving an active command for a first row from a memory controller, reading a first count from a per-row hammer tracking (PRHT) region of the first row, updating the first count to generate a first updated count, comparing the first updated count with one of first and second thresholds to generate a comparison result, wherein when the first row is adjacent to the given row, the first updated count is compared with the first threshold and when the first row is not adjacent to the given row, the first updated count is compared with the second threshold, outputting a target row address based on the comparison result, and performing a row hammer mitigation operation on a row corresponding to the target row address.

公开(公告)号：US10366021B2

公开(公告)日：2019-07-30

申请号：US15390063

申请日：2016-12-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungup Moon ,  Tae-Kyeong Ko ,  Do-Han Kim ,  Jongmin Park ,  Kyoyeon Won

IPC: G06F13/16 ,  G06F12/08 ,  G06F12/0804 ,  G06F13/40 ,  G06F12/0868

Abstract: A memory system includes a nonvolatile memory electrically connected to a data bus, a DRAM electrically connected to the data bus, and a memory controller configured to drive the DRAM as a cache memory and the nonvolatile memory as a main memory and to synchronize data of a cache line with data of the nonvolatile memory in units of cache units based on a dirty flag. The DRAM is configured to load data of the cache line that caches data stored in the nonvolatile memory and to store the dirty flag, which indicates whether a cache unit is dirty, in units of cache units, where a size of each cache unit is smaller than a size of the cache line.

公开(公告)号：US09037783B2

公开(公告)日：2015-05-19

申请号：US13713377

申请日：2012-12-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Wan Koh ,  Tae-Kyeong Ko

IPC: G06F12/02 ,  G11C5/00

CPC classification number: G06F12/0246 ,  G06F2212/7208 ,  G11C5/00

Abstract: A non-volatile memory device having respective parallel queues is disclosed. The non-volatile memory device includes a plurality of concurrently addressable units. The non-volatile memory device has respective queues for the concurrently addressable units, and transfers a second command to respective queues for the remaining concurrently addressable units while a first command is executed in a part of the concurrently addressable units, and executes a second command in the remaining concurrently addressable units. Accordingly, non-volatile memory device may concurrently access the concurrently addressable units in parallel, and may have high speed.

Abstract translation: 公开了具有各自的并行队列的非易失性存储器件。 非易失性存储器件包括多个可同时寻址的单元。 非易失性存储器件具有用于同时可寻址单元的各自的队列，并且在同时可寻址单元的一部分中执行第一命令时，将第二命令传送到剩余的可寻址单元的各个队列，并且执行第二命令 剩余的可寻址单元。 因此，非易失性存储装置可以并行地同时访问同时可寻址单元，并且可以具有高速度。

公开(公告)号：US20240177746A1

公开(公告)日：2024-05-30

申请号：US18209057

申请日：2023-06-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chinam Kim ,  Tae-Kyeong Ko ,  Cholmin Kim

IPC: G11C7/10

CPC classification number: G11C7/1039 ,  G11C7/1069 ,  G11C7/1096

Abstract: A semiconductor memory system includes a memory device including plural banks, and a memory controller that generates an offset address for a first bank among the plural banks and a command indicating the offset address, based on a first request. The memory device generates a first address by adding the offset address to a base address for the first bank, according to the command, and performs a memory operation on the first address of the first bank according to the command.