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    Memory device for supporting command bus training mode and method of operating the same
    1.
    发明授权
    Memory device for supporting command bus training mode and method of operating the same 有权

    公开(公告)号：US10720197B2

    公开(公告)日：2020-07-21

    申请号：US16196777

    申请日：2018-11-20

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Young-hun Kim ,  Si-hong Kim ,  Tae-young Oh ,  Kyung-soo Ha

    IPC: G11C7/22 ,  G11C7/10 ,  G11C8/18 ,  G11C8/10 ,  G11C29/50 ,  G11C29/02

    Abstract: There are provided, a memory device for supporting a command bus training (CBT) mode and a method of operating the same. The memory device is configured to enter a CBT mode or exit from the CBT mode in response to a logic level of a first data signal, which is not included in second data signals, which are in one-to-one correspondence with command/address signals, which are used to output a CBT pattern in the CBT mode. The memory device is further configured to change a reference voltage value in accordance with a second reference voltage setting code received by terminals associated with the second data signals, to terminate the command/address signals or a pair of data clock signals to a resistance value corresponding to an on-die termination (ODT) code setting stored in a mode register, and to turn off ODT of data signals in the CBT mode.

    METHOD OF REFRESHING MEMORY DEVICE
    2.
    发明申请
    METHOD OF REFRESHING MEMORY DEVICE 有权
    刷新存储器件的方法

    公开(公告)号：US20170069371A1

    公开(公告)日：2017-03-09

    申请号：US15258174

    申请日：2016-09-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seung-jun Shin ,  Tae-young Oh ,  Kwang-il Park

    IPC: G11C11/406

    CPC classification number: G11C11/40615

    Abstract: A method of refreshing a memory device includes performing normal refresh operations on memory cell rows in response to a refresh command and performing self-refresh operations on the memory cell rows according to a refresh clock signal in response during a self-refresh mode of the memory device between a self-refresh enter command and a self-refresh exit command. The refresh clock signal has a first self-refresh cycle before the self-refresh begins and a second self-refresh cycle, which may be longer than the first self-refresh cycle, after the self-refresh begins. In some examples, no self-refresh may be performed by the memory device during a self-refresh mode.

    Abstract translation: 刷新存储器件的方法包括响应于刷新命令对存储器单元行执行正常刷新操作，并且在存储器的自刷新模式期间响应于刷新时钟信号对存储器单元行执行自刷新操作 设备在自刷新输入命令和自刷新退出命令之间。 刷新时钟信号在自刷新开始之前具有第一自刷新周期，并且在自刷新开始之后具有可能比第一自刷新周期长的第二自刷新周期。 在一些示例中，在自刷新模式期间，存储器件不能执行自刷新。

    MEMORY DEVICE FOR SUPPORTING COMMAND BUS TRAINING MODE AND METHOD OF OPERATING THE SAME
    3.
    发明申请
    MEMORY DEVICE FOR SUPPORTING COMMAND BUS TRAINING MODE AND METHOD OF OPERATING THE SAME 有权

    公开(公告)号：US20250149076A1

    公开(公告)日：2025-05-08

    申请号：US19018469

    申请日：2025-01-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Young-hun Kim ,  Si-hong Kim ,  Tae-young Oh ,  Kyung-soo Ha

    IPC: G11C7/22 ,  G11C7/10 ,  G11C8/10 ,  G11C8/18 ,  G11C29/02 ,  G11C29/50

    Abstract: There are provided a memory device for supporting a command bus training (CBT) mode and a method of operating the same. The memory device is configured to enter a CBT mode or exit from the CBT mode in response to a logic level of a first data signal, which is not included in second data signals, which are in one-to-one correspondence with command/address signals, which are used to output a CBT pattern in the CBT mode. The memory device is further configured to change a reference voltage value in accordance with a second reference voltage setting code received by terminals associated with the second data signals, to terminate the command/address signals or a pair of data clock signals to a resistance value corresponding to an on-die termination (ODT) code setting stored in a mode register, and to turn off ODT of data signals in the CBT mode.

    MEMORY DEVICE FOR SUPPORTING COMMAND BUS TRAINING MODE AND METHOD OF OPERATING THE SAME
    4.
    发明申请
    MEMORY DEVICE FOR SUPPORTING COMMAND BUS TRAINING MODE AND METHOD OF OPERATING THE SAME 有权

    公开(公告)号：US20250124959A1

    公开(公告)日：2025-04-17

    申请号：US19002120

    申请日：2024-12-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Young-hun Kim ,  Si-hong Kim ,  Tae-young Oh ,  Kyung-soo Ha

    IPC: G11C7/22 ,  G11C7/10 ,  G11C8/10 ,  G11C8/18 ,  G11C29/02 ,  G11C29/50

    Abstract: There are provided a memory device for supporting a command bus training (CBT) mode and a method of operating the same. The memory device is configured to enter a CBT mode or exit from the CBT mode in response to a logic level of a first data signal, which is not included in second data signals, which are in one-to-one correspondence with command/address signals, which are used to output a CBT pattern in the CBT mode. The memory device is further configured to change a reference voltage value in accordance with a second reference voltage setting code received by terminals associated with the second data signals, to terminate the command/address signals or a pair of data clock signals to a resistance value corresponding to an on-die termination (ODT) code setting stored in a mode register, and to turn off ODT of data signals in the CBT mode.

    MEMORY MODULE AND SEMICONDUCTOR MEMORY SYSTEM INCLUDING THE SAME
    7.
    发明申请
    MEMORY MODULE AND SEMICONDUCTOR MEMORY SYSTEM INCLUDING THE SAME 审中-公开

    公开(公告)号：US20170097790A1

    公开(公告)日：2017-04-06

    申请号：US15194963

    申请日：2016-06-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Su-yeon Doo ,  Tae-young Oh ,  Kwang-il Park

    IPC: G06F3/06 ,  G06F13/16

    CPC classification number: G06F13/1668 ,  G06F3/061 ,  G06F3/0635 ,  G06F3/0659 ,  G06F3/0688

    Abstract: A memory module includes a first memory group including a plurality of first semiconductor memory devices, and a second memory group including a plurality of second semiconductor memory devices. The first semiconductor memory devices and the second semiconductor memory devices share a command/address bus. The first semiconductor memory devices perform a first operation in response to a command signal received by the first semiconductor memory devices from the command/address bus and the second semiconductor memory devices perform a second operation, different from the first operation, in response to the same command signal received by the second semiconductor memory devices from the command/address bus.

    Method of refreshing memory device
    9.
    发明授权
    Method of refreshing memory device 有权

    公开(公告)号：US09767882B2

    公开(公告)日：2017-09-19

    申请号：US15258174

    申请日：2016-09-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seung-jun Shin ,  Tae-young Oh ,  Kwang-il Park

    IPC: G11C7/00 ,  G11C11/406

    CPC classification number: G11C11/40615

    Abstract: A method of refreshing a memory device includes performing normal refresh operations on memory cell rows in response to a refresh command and performing self-refresh operations on the memory cell rows according to a refresh clock signal in response during a self-refresh mode of the memory device between a self-refresh enter command and a self-refresh exit command. The refresh clock signal has a first self-refresh cycle before the self-refresh begins and a second self-refresh cycle, which may be longer than the first self-refresh cycle, after the self-refresh begins. In some examples, no self-refresh may be performed by the memory device during a self-refresh mode.

    Memory device for supporting command bus training mode and method of operating the same
    10.
    发明授权
    Memory device for supporting command bus training mode and method of operating the same 有权

    公开(公告)号：US12217823B2

    公开(公告)日：2025-02-04

    申请号：US18332325

    申请日：2023-06-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Young-hun Kim ,  Si-hong Kim ,  Tae-young Oh ,  Kyung-soo Ha

    IPC: G11C7/22 ,  G11C7/10 ,  G11C8/10 ,  G11C8/18 ,  G11C29/02 ,  G11C29/50

    Abstract: There are provided a memory device for supporting a command bus training (CBT) mode and a method of operating the same. The memory device is configured to enter a CBT mode or exit from the CBT mode in response to a logic level of a first data signal, which is not included in second data signals, which are in one-to-one correspondence with command/address signals, which are used to output a CBT pattern in the CBT mode. The memory device is further configured to change a reference voltage value in accordance with a second reference voltage setting code received by terminals associated with the second data signals, to terminate the command/address signals or a pair of data clock signals to a resistance value corresponding to an on-die termination (ODT) code setting stored in a mode register, and to turn off ODT of data signals in the CBT mode.

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