公开(公告)号：US20230022545A1

公开(公告)日：2023-01-26

申请号：US17680507

申请日：2022-02-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： EUI BOK LEE ,  WANDON KIM ,  RAKHWAN KIM

IPC: H01L23/522 ,  H01L29/417 ,  H01L21/768

Abstract: Disclosed are a semiconductor device and a method of fabricating the same. The device includes an FEOL layer, which includes a plurality of individual devices, on a substrate, and first, second, and third metal layers sequentially stacked on the FEOL layer. The second metal layer includes an interlayer insulating layer and an interconnection line in the interlayer insulating layer. The interconnection line includes a lower via portion electrically connected to the first metal layer, an upper via portion electrically connected to the third metal layer, and a line portion between the lower via portion and the upper via portion. A line width of an upper portion of the interconnection line gradually decreases in a vertical direction away from the substrate, and a line width of a lower portion of the interconnection line gradually increases in a vertical direction away from the substrate.

公开(公告)号：US20220344514A1

公开(公告)日：2022-10-27

申请号：US17862961

申请日：2022-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： WEONHONG KIM ,  WANDON KIM ,  HYEONJUN BAEK ,  SANGJIN HYUN

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/786 ,  H01L21/28

Abstract: A semiconductor device includes a substrate including an active pattern, a gate electrode crossing the active pattern in a plan view, and a ferroelectric pattern interposed between the active pattern and the gate electrode. The gate electrode includes a work function metal pattern disposed on the ferroelectric pattern, and an electrode pattern filling a recess formed in an upper portion of the work function metal pattern. A top surface of a topmost portion of the ferroelectric pattern is lower than a bottom surface of the recess.

公开(公告)号：US20220085183A1

公开(公告)日：2022-03-17

申请号：US17531903

申请日：2021-11-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： BYOUNGHOON LEE ,  JONGHO PARK ,  WANDON KIM ,  SANGJIN HYUN

IPC: H01L29/49 ,  H01L27/088 ,  H01L29/78 ,  H01L29/51 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device includes a substrate having first and second active regions, first and second active patterns on the first and second active regions, first and second gate electrodes running across the first and second active patterns, and a high-k dielectric layer between the first active pattern and the first gate electrode and between the second active pattern and the second gate electrode. The first gate electrode includes a work function metal pattern and an electrode pattern. The second gate electrode includes a first work function metal pattern, a second work function metal pattern, and an electrode pattern. The first work function metal pattern contains the same impurity as that of the high-k dielectric layer. An impurity concentration of the first work function metal pattern of the second gate electrode is greater than that of the work function metal pattern of the first gate electrode.

公开(公告)号：US20220208673A1

公开(公告)日：2022-06-30

申请号：US17344670

申请日：2021-06-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： EUI BOK LEE ,  RAKHWAN KIM ,  WANDON KIM ,  SEOWOO NAM ,  SUNYOUNG NOH ,  KI CHUL PARK ,  JONGCHAN SHIN ,  MINJOO LEE ,  HYUNBAE LEE ,  SEUNGSEOK HA

IPC: H01L23/522 ,  H01L29/417 ,  H01L29/78 ,  H01L27/088

Abstract: Disclosed is a semiconductor device including a substrate, a first interlayer dielectric layer on the substrate, a plurality of first vias in the first interlayer dielectric layer, a second interlayer dielectric layer on the first interlayer dielectric layer, and a first power line and a first lower line in the second interlayer dielectric layer that are electrically connected to respective ones of the first vias. A first width in a first direction of the first power line is greater than a second width in the first direction of the first lower line. The first power line includes a first metallic material. The first lower line includes a second metallic material. The first vias includes a third metallic material. The first, second, and third metallic materials are different from each other.

公开(公告)号：US20210005729A1

公开(公告)日：2021-01-07

申请号：US17024813

申请日：2020-09-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： JONGHAN LEE ,  WANDON KIM ,  JAEYEOL SONG ,  JEONGHYUK YIM ,  HYUNGSUK JUNG

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/51 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/768

Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a gate electrode on a substrate, an upper capping pattern on the gate electrode, and a lower capping pattern between the gate electrode and the upper capping pattern. The lower capping pattern comprises a first portion between the gate electrode and the upper capping pattern, and a plurality of second portions extending from the first portion onto corresponding side surfaces of the upper capping pattern. The upper capping pattern covers a topmost surface of each of the second portions.

公开(公告)号：US20190165114A1

公开(公告)日：2019-05-30

申请号：US15990983

申请日：2018-05-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： JONGHAN LEE ,  WANDON KIM ,  JAEYEOL SONG ,  JEONGHYUK YIM ,  HyungSuk JUNG

IPC: H01L29/423 ,  H01L21/28 ,  H01L29/51 ,  H01L27/088

Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a gate electrode on a substrate, an upper capping pattern on the gate electrode, and a lower capping pattern between the gate electrode and the upper capping pattern. The lower capping pattern comprises a first portion between the gate electrode and the upper capping pattern, and a plurality of second portions extending from the first portion onto corresponding side surfaces of the upper capping pattern. The upper capping pattern covers a topmost surface of each of the second portions.

公开(公告)号：US20240113163A1

公开(公告)日：2024-04-04

申请号：US18130732

申请日：2023-04-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： GEUNWOO KIM ,  WANDON KIM ,  HYUNWOO KANG ,  HYUNBAE LEE ,  JEONGHYUK YIM

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L27/092 ,  H01L29/42392 ,  H01L29/6656 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes; a substrate including an active pattern, a channel pattern and a source/drain pattern on the active pattern, wherein the channel pattern is connected to the source/drain pattern, a gate electrode on the channel pattern, and a gate contact connected to a top surface of the gate electrode, wherein the gate contact includes a capping layer directly contacting the top surface of the gate electrode and a metal layer on the capping layer, wherein the capping layer and the metal layer include the same metal, a concentration of oxygen in the metal layer ranges from between about 2 at % to about 10 at %, and a maximum concentration of oxygen in the capping layer ranges from between about 15 at % to about 30 at %.

公开(公告)号：US20220302115A1

公开(公告)日：2022-09-22

申请号：US17831861

申请日：2022-06-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JONGHO PARK ,  JAEYEOL SONG ,  WANDON KIM ,  BYOUNGHOON LEE ,  MUSARRAT HASAN

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/161 ,  H01L29/417 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor device includes first and second active patterns on first and second active regions of a substrate, respectively, a pair of first source/drain patterns and a first channel pattern therebetween which are in an upper portion of the first active pattern, a pair of second source/drain patterns and a second channel pattern therebetween which are in an upper portion of the second active pattern, and first and second gate electrodes intersecting the first and second channel patterns, respectively. Each of the first and second gate electrodes includes a first metal pattern adjacent to a corresponding one of the first and second channel patterns. The first and second channel patterns include SiGe. A Ge concentration of the second channel pattern is higher than a Ge concentration of the first channel pattern. A thickness of the first metal pattern of the second gate electrode is greater than a thickness of the first metal pattern of the first gate electrode.

公开(公告)号：US20210167214A1

公开(公告)日：2021-06-03

申请号：US17176248

申请日：2021-02-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： WEONHONG KIM ,  WANDON KIM ,  HYEONJUN BAEK ,  SANGJIN HYUN

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/49 ,  H01L21/28 ,  H01L29/66 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06

Abstract: A semiconductor device includes a substrate including an active pattern, a gate electrode crossing the active pattern in a plan view, and a ferroelectric pattern interposed between the active pattern and the gate electrode. The gate electrode includes a work function metal pattern disposed on the ferroelectric pattern, and an electrode pattern filling a recess formed in an upper portion of the work function metal pattern. A top surface of a topmost portion of the ferroelectric pattern is lower than a bottom surface of the recess.

公开(公告)号：US20200013899A1

公开(公告)日：2020-01-09

申请号：US16503790

申请日：2019-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： WEONHONG KIM ,  WANDON KIM ,  HYEONJUN BAEK ,  SANGJIN HYUN

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/786 ,  H01L21/28 ,  H01L29/66

Abstract: A semiconductor device includes a substrate including an active pattern, a gate electrode crossing the active pattern in a plan view, and a ferroelectric pattern interposed between the active pattern and the gate electrode. The gate electrode includes a work function metal pattern disposed on the ferroelectric pattern, and an electrode pattern filling a recess formed in an upper portion of the work function metal pattern. A top surface of a topmost portion of the ferroelectric pattern is lower than a bottom surface of the recess.