公开(公告)号：US10103163B2

公开(公告)日：2018-10-16

申请号：US15249389

申请日：2016-08-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Hoon Son ,  Jin-I Lee ,  Kyunghyun Kim ,  Byeongju Kim ,  Phil Ouk Nam ,  Kwangchul Park ,  Yeon-Sil Sohn ,  JongHeun Lim ,  Wonbong Jung

IPC: H01L29/41 ,  H01L27/11582 ,  H01L27/1157 ,  H01L29/792 ,  H01L29/66 ,  H01L29/40 ,  H01L29/423

Abstract: A semiconductor memory device is disclosed. The device may include a stack including gate electrodes stacked on a substrate in a vertical direction and insulating patterns interposed between the gate electrodes, vertical channels passing through the stack and connected to the substrate, a tunnel insulating layer enclosing each of the vertical channels, charge storing patterns provided between the tunnel insulating layer and the gate electrodes and spaced apart from each other in the vertical direction, blocking insulating patterns provided between the charge storing patterns and the gate electrodes and spaced apart from each other in the vertical direction, and a bit line crossing the stack and connected to the vertical channels. The blocking insulating patterns may have a vertical thickness that is greater than that of the gate electrodes.

公开(公告)号：US09905568B2

公开(公告)日：2018-02-27

申请号：US15251580

申请日：2016-08-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong-Hoon Son ,  Jong-Won Kim ,  Chang-Seok Kang ,  Young-Woo Park ,  Jae-Duk Lee ,  Kyung-Hyun Kim ,  Byeong-Ju Kim ,  Phil-Ouk Nam ,  Kwang-Chul Park ,  Yeon-Sil Sohn ,  Jin-I Lee ,  Won-Bong Jung

IPC: H01L27/115 ,  H01L29/66 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11582

CPC classification number: H01L27/1157 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/66833

Abstract: A nonvolatile memory device includes a conductive line disposed on a substrate and vertically extended from the substrate, a first channel layer disposed on the substrate and vertically extended from the substrate, wherein the first channel layer is spaced apart from the conductive line, a second channel layer vertically extended from the substrate, wherein the second channel layer is disposed between the first channel layer and the conductive line, a first gate electrode disposed between the conductive line and the second channel layer, wherein the first gate electrode includes a first portion having a first thickness and a second portion having a second thickness that is different from the first thickness, and a second gate electrode disposed between the first channel layer and the second channel layer, wherein the second gate electrode has the second thickness.

公开(公告)号：US09716181B2

公开(公告)日：2017-07-25

申请号：US15176611

申请日：2016-06-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Phil Ouk Nam ,  Yong-Hoon Son ,  Kyunghyun Kim ,  Byeongju Kim ,  Kwangchul Park ,  Yeon-Sil Sohn ,  Jin-l Lee ,  JongHeun Lim ,  Wonbong Jung

IPC: H01L29/04 ,  H01L29/10 ,  H01L31/036 ,  H01L29/786 ,  H01L27/12

CPC classification number: H01L29/78672 ,  H01L27/0688 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/1207 ,  H01L29/78642

Abstract: A semiconductor device includes a polycrystalline semiconductor layer on a substrate, first and second stacks on the polycrystalline semiconductor layer, the first and second stacks extending in a first direction, a separation trench between the first and second stacks and extending in the first direction, the separation trench separating the first and second stacks in a second direction crossing the first direction, and vertical channel structures vertically passing through each of the first and second stacks, wherein the polycrystalline semiconductor layer includes a first grain region and a second grain region in contact with each other, the first and second grain region being adjacent to each other along the second direction, and wherein each of the first and second grain regions includes a plurality of crystal grains, each crystal grain having a longitudinal axis parallel to the second direction.

公开(公告)号：US09711523B2

公开(公告)日：2017-07-18

申请号：US14574456

申请日：2014-12-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonggil Lee ,  Yeon-Sil Sohn ,  Woonghee Sohn ,  Kihyun Yoon ,  Myoungbum Lee ,  Tai-Soo Lim ,  Yong Chae Jung

IPC: H01L27/11582

CPC classification number: H01L27/11582

Abstract: Provided is a semiconductor device, including gate structures on a substrate, the gate structures extending parallel to a first direction and being spaced apart from each other by a separation trench interposed therebetween, each of the gate structures including insulating patterns stacked on the substrate and a gate electrode interposed therebetween; vertical pillars connected to the substrate through the gate structures; an insulating spacer in the separation trench covering a sidewall of each of the gate structures; and a diffusion barrier structure between the gate electrode and the insulating spacer.

公开(公告)号：US09312270B2

公开(公告)日：2016-04-12

申请号：US14593221

申请日：2015-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Tae Jang ,  Myoungbum Lee ,  Seungmok Shin ,  JinGyun Kim ,  Yeon-Sil Sohn ,  Seung-Yup Lee ,  Dae-Hun Choi

IPC: H01L21/00 ,  H01L27/115 ,  H01L21/28 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L21/8239 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31111 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11578 ,  H01L27/11582

Abstract: Methods of manufacturing a three-dimensional semiconductor device are provided. The method includes: forming a thin film structure, where first and second material layers of at least 2n (n is an integer more than 2) are alternately and repeatedly stacked, on a substrate; wherein the first material layer applies a stress in a range of about 0.1×109 dyne/cm2 to about 10×109 dyne/cm2 to the substrate and the second material layer applies a stress in a range of about −0.1×109 dyne/cm2 to about −10×109 dyne/cm2 to the substrate.

Abstract translation: 提供制造三维半导体器件的方法。 该方法包括：在基板上形成薄膜结构，其中至少2n（n是大于2的整数）的第一和第二材料层交替重复堆叠; 其中所述第一材料层向所述基板施加约0.1×10 9达因/ cm 2至约10×10 9达因/ cm 2的范围内的应力，并且所述第二材料层施加约-0.1×109达因/ cm2的范围内的应力 至约-10×109达因/平方厘米。