公开(公告)号：US11854912B2

公开(公告)日：2023-12-26

申请号：US17196538

申请日：2021-03-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joonsung Kim ,  Yonghwan Kwon ,  Sanguk Kim

IPC: H01L21/66 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L22/32 ,  H01L23/3128 ,  H01L24/05 ,  H01L24/24 ,  H01L2224/022 ,  H01L2224/24226

Abstract: A semiconductor package is provided. The semiconductor package includes a chip pad of a semiconductor chip, the chip pad including a connection portion and a test portion in a first surface of the chip pad; a barrier layer covering the chip pad, the barrier layer defining a first opening and a second opening that is separate from the first opening, the first opening exposing the connection portion of the chip pad, and the second opening exposing the test portion of the chip pad; and a redistribution structure.

公开(公告)号：US11545440B2

公开(公告)日：2023-01-03

申请号：US17019519

申请日：2020-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghwan Kwon

IPC: H01L23/538 ,  H01L23/31 ,  H01L25/10 ,  H01L23/00

Abstract: A semiconductor package includes a redistribution substrate including a first redistribution layer, a first molding member on the redistribution substrate, a second redistribution layer on an upper surface of the first molding member and having a redistribution pad, an electrical connection pad on an upper surface of a second molding member and electrically connected to the second redistribution layer, and a passivation layer on the second molding member and having an opening exposing at least a portion of the electrical connection pad. The electrical connection pad includes a conductor layer, including a first metal, and a contact layer on the conductor layer and including a second metal. The redistribution pad includes a third metal, different from the first metal and the second metal. The portion of the electrical connection pad, exposed by the opening, has a width greater than a width of the redistribution pad.

公开(公告)号：US09018041B2

公开(公告)日：2015-04-28

申请号：US14064467

申请日：2013-10-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Han-shin Youn ,  Yonghwan Kwon ,  YoungHoon Ro ,  Woojae Kim ,  Sungwoo Park

IPC: H01L21/58 ,  H01L23/00 ,  H01L23/498 ,  H01L25/10 ,  H01L25/16 ,  H01L21/56

CPC classification number: H01L24/03 ,  H01L21/563 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/48 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/0401 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/50 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An example embodiment relates to a semiconductor package. The semiconductor package includes a first substrate including a first pad, a second substrate upwardly spaced apart from the first substrate and including a second pad opposite to the first pad. At least one electrode is coupled between the first pad and the second pad. The semiconductor package includes a guide ring formed at a periphery of the electrode between the first substrate and the second substrate.

Abstract translation: 示例性实施例涉及半导体封装。 半导体封装包括第一衬底，其包括第一焊盘，与第一衬底向上间隔开的第二衬底，并且包括与第一焊盘相对的第二焊盘。 至少一个电极耦合在第一焊盘和第二焊盘之间。 半导体封装包括形成在第一基板和第二基板之间的电极的周边处的引导环。

公开(公告)号：US11996378B2

公开(公告)日：2024-05-28

申请号：US17646675

申请日：2021-12-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yonghwan Kwon ,  Yongjin Park

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L24/08 ,  H01L23/3107 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/08235

Abstract: A semiconductor package includes a first redistribution structure, including a first insulating layer and a first redistribution layer disposed below the first insulating layer; a semiconductor chip disposed on the first redistribution structure, including a connection terminal electrically connected to the first redistribution layer and buried in the first insulating layer; an encapsulant disposed on the first redistribution structure that seals a portion of the semiconductor chip; a second redistribution structure, including a second redistribution layer disposed on the encapsulant; and a through via, including a pattern portion buried in the first insulating layer and electrically connected to the first redistribution layer and a via portion penetrating through the encapsulant and electrically connecting the pattern portion and the second redistribution layer. The connection terminal and the pattern portion are located at a first level and are electrically connected to each other at a second level lower than the first level.

公开(公告)号：US11853640B2

公开(公告)日：2023-12-26

申请号：US17140311

申请日：2021-01-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyeonji Lee ,  Yonghwan Kwon ,  Soyoung Shin ,  Jisoo Yoon ,  Hajeong Yun ,  Sangjoon Lee ,  Eunjin Lee

IPC: G06F3/16 ,  H04N21/41 ,  H04R3/12

CPC classification number: G06F3/16 ,  H04N21/41265 ,  H04R3/12 ,  H04R2420/07

Abstract: Provided is a display apparatus including: a display; a content interface; a communication interface; and a controller configured to: control the display to display an image corresponding to the broadcast signal received through the content interface; receive operation information of an external audio apparatus through at least one interface selected from the content interface and the communication interface; and control the display to display a control menu for providing the operation information of the external audio apparatus and acquiring a user input related to an operation of the external audio apparatus in response to the operation information of the external audio apparatus being received.

公开(公告)号：US11545422B2

公开(公告)日：2023-01-03

申请号：US17225178

申请日：2021-04-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghwan Kwon

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/18 ,  H01L23/00

Abstract: A fan-out semiconductor package includes: a support wiring structure including a support wiring conductive structure, a plurality of support wiring insulating layers including a first support wiring insulating layer having a recess area and a second support wiring insulating layer on the first support wiring insulating layer and enveloping the support wiring conductive structure, a pad layer enveloped by the second support wiring insulating layer and connected to the support wiring conductive structure, and an under-bump metallurgy (UBM) layer enveloped by the first support wiring insulating layer and connected to the pad layer; and a semiconductor chip on the support wiring structure, wherein the UBM layer includes a body portion and a protrusion protruding from the body portion and arranged in the recess area.

公开(公告)号：US10734367B2

公开(公告)日：2020-08-04

申请号：US16232159

申请日：2018-12-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Kwan Ryu ,  Yonghwan Kwon ,  Yun Seok Choi ,  Chajea Jo ,  Taeje Cho

IPC: H01L25/10 ,  H01L23/00 ,  H01L25/03 ,  H01L23/538 ,  H01L23/31 ,  H01L25/00 ,  H01L21/56

Abstract: A semiconductor package includes upper and lower semiconductor chip packages, and a redistribution wiring layer pattern interposed between the packages. The lower package includes a molding layer in which at least one chip is embedded, and has a top surface and an inclined sidewall surface along which the redistribution wiring layer pattern is formed. The upper and lower packages are electrically connected to through the redistribution wiring layer pattern. A first package may be formed by a wafer level packaging technique and may include a redistribution wiring layer as a substrate, a semiconductor chip disposed on the redistribution wiring layer, and a molding layer on which the lower package, redistribution wiring layer pattern and upper package are disposed.

公开(公告)号：US12261103B2

公开(公告)日：2025-03-25

申请号：US17647144

申请日：2022-01-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yonghwan Kwon

IPC: H01L23/48 ,  H01L23/31 ,  H01L23/498 ,  H01L25/10 ,  H01L23/00

Abstract: A semiconductor package includes a semiconductor chip on a first redistribution substrate, a molding layer that covers the semiconductor chip, and a second redistribution substrate on the molding layer and that includes a dielectric layer, a redistribution pattern, and a conductive pad. The dielectric layer includes a lower opening that exposes the conductive pad, and an upper opening connected to the lower opening and that is wider than the lower opening. The semiconductor package also comprises a redistribution pad on the conductive pad and that covers a sidewall of the lower opening and a bottom surface of the upper opening. A top surface of the dielectric layer is located at a higher level than a top surface of the redistribution pad. The top surface of the redistribution pad is located on the bottom surface of the upper opening.

公开(公告)号：US20220375889A1

公开(公告)日：2022-11-24

申请号：US17646675

申请日：2021-12-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghwan Kwon ,  Yongjin Park

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/31

Abstract: A semiconductor package includes a first redistribution structure, including a first insulating layer and a first redistribution layer disposed below the first insulating layer; a semiconductor chip disposed on the first redistribution structure, including a connection terminal electrically connected to the first redistribution layer and buried in the first insulating layer; an encapsulant disposed on the first redistribution structure that seals a portion of the semiconductor chip; a second redistribution structure, including a second redistribution layer disposed on the encapsulant; and a through via, including a pattern portion buried in the first insulating layer and electrically connected to the first redistribution layer and a via portion penetrating through the encapsulant and electrically connecting the pattern portion and the second redistribution layer. The connection terminal and the pattern portion are located at a first level and are electrically connected to each other at a second level lower than the first level.

公开(公告)号：US20220102256A1

公开(公告)日：2022-03-31

申请号：US17225178

申请日：2021-04-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghwan Kwon

IPC: H01L23/498 ,  H01L23/538 ,  H01L25/18 ,  H01L23/00

Abstract: A fan-out semiconductor package includes: a support wiring structure including a support wiring conductive structure, a plurality of support wiring insulating layers including a first support wiring insulating layer having a recess area and a second support wiring insulating layer on the first support wiring insulating layer and enveloping the support wiring conductive structure, a pad layer enveloped by the second support wiring insulating layer and connected to the support wiring conductive structure, and an under-bump metallurgy (UBM) layer enveloped by the first support wiring insulating layer and connected to the pad layer; and a semiconductor chip on the support wiring structure, wherein the UBM layer includes a body portion and a protrusion protruding from the body portion and arranged in the recess area.