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    Package module
    1.
    发明授权
    Package module 有权

    公开(公告)号：US11842950B2

    公开(公告)日：2023-12-12

    申请号：US17685227

    申请日：2022-03-02

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yongjin Park ,  Myungsam Kang ,  Younggwan Ko

    IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522

    CPC classification number: H01L23/49534 ,  H01L23/3157 ,  H01L23/49531 ,  H01L23/49537 ,  H01L23/5226 ,  H01L24/09 ,  H01L2224/02372 ,  H01L2224/02377 ,  H01L2224/02379

    Abstract: A package module includes a connection structure including one or more redistribution layers, a semiconductor chip disposed on the connection structure and having a connection pad electrically connected to the one or more redistribution layers, a plurality of electronic components disposed on the connection structure and electrically connected to the one or more redistribution layers, one or more frames disposed on the connection structure, and an encapsulant disposed on the connection structure, and respectively covering at least portions of the semiconductor chip, the plurality of electronic components, and the one or more frames. At least a portion of an outer side surface of the encapsulant is coplanar on the same level as at least a portion of an outer side surface of at least one of the one or more frames.

    SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE
    2.
    发明公开
    SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE 审中-公开

    公开(公告)号：US20240290739A1

    公开(公告)日：2024-08-29

    申请号：US18655471

    申请日：2024-05-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yonghwan Kwon ,  Yongjin Park

    IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498

    CPC classification number: H01L24/08 ,  H01L23/3107 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/08235

    Abstract: A semiconductor package includes a first redistribution structure, including a first insulating layer and a first redistribution layer disposed below the first insulating layer; a semiconductor chip disposed on the first redistribution structure, including a connection terminal electrically connected to the first redistribution layer and buried in the first insulating layer; an encapsulant disposed on the first redistribution structure that seals a portion of the semiconductor chip; a second redistribution structure, including a second redistribution layer disposed on the encapsulant; and a through via, including a pattern portion buried in the first insulating layer and electrically connected to the first redistribution layer and a via portion penetrating through the encapsulant and electrically connecting the pattern portion and the second redistribution layer. The connection terminal and the pattern portion are located at a first level and are electrically connected to each other at a second level lower than the first level.

    Semiconductor packages
    5.
    发明授权
    Semiconductor packages 有权

    公开(公告)号：US11444070B2

    公开(公告)日：2022-09-13

    申请号：US17200984

    申请日：2021-03-15

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yongjin Park ,  Jiin Yu ,  Jin-San Jung

    IPC: H01L25/18 ,  H01L23/00 ,  H01L23/48

    Abstract: A semiconductor package may include a first semiconductor chip, a second semiconductor chip on the first semiconductor chip, and an adhesive layer between the first semiconductor chip and the second semiconductor chip. The first semiconductor chip may include a semiconductor substrate and a plurality of protection layers on the semiconductor substrate. The topmost layer of the protection layers may have a top surface with convex portions and concave portions, and the convex portions and the concave portions may be in contact with the adhesive layer.

    SEMICONDUCTOR PACKAGE
    6.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20210118765A1

    公开(公告)日：2021-04-22

    申请号：US16917251

    申请日：2020-06-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Myungsam Kang ,  Yongjin Park ,  Youngchan Ko

    IPC: H01L23/367 ,  H01L23/31 ,  H01L23/538 ,  H01L23/552 ,  H01L23/00 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56

    Abstract: A semiconductor package includes an interconnect structure having a first surface and a second surface opposing the first surface, and including a redistribution pattern and a vertical connection conductor, a first semiconductor chip disposed for a first inactive surface to oppose the first surface, a second semiconductor chip disposed on the first surface of the interconnect structure and disposed for the second inactive surface to oppose the first surface; a first encapsulant encapsulating the first and second semiconductor chips, a backside wiring layer disposed on the first encapsulant, a wiring structure connecting the redistribution pattern to the backside wiring layer, a heat dissipation member disposed on the second surface and connected to the vertical connection conductor.

    Semiconductor device and semiconductor package having the same
    7.
    发明授权
    Semiconductor device and semiconductor package having the same 有权

    公开(公告)号：US12154840B2

    公开(公告)日：2024-11-26

    申请号：US18310284

    申请日：2023-05-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seonho Lee ,  Jinsu Kim ,  Junwoo Myung ,  Yongjin Park ,  Jaekul Lee

    IPC: H01L23/373 ,  H01L23/053 ,  H01L23/31 ,  H01L23/498

    Abstract: A semiconductor device including a semiconductor chip having a first surface and a second surface opposite to the first surface, a first heat dissipation member on the second surface of the semiconductor chip, the first heat dissipation member having a vertical thermal conductivity in a direction perpendicular to the second surface, and a horizontal thermal conductivity in a direction parallel to the second surface, the first vertical thermal conductivity being smaller than the first horizontal thermal conductivity, and a second heat dissipation member comprising a vertical pattern penetrating the first heat dissipation member, the second heat dissipation member having a vertical thermal conductivity that is greater than the vertical thermal conductivity of the first heat dissipation member may be provided.

    Fan-out type semiconductor package and method of manufacturing the same
    8.
    发明授权
    Fan-out type semiconductor package and method of manufacturing the same 有权

    公开(公告)号：US12002798B2

    公开(公告)日：2024-06-04

    申请号：US17861359

    申请日：2022-07-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Myungsam Kang ,  Youngchan Ko ,  Yongjin Park

    IPC: H01L25/065 ,  H01L25/18

    CPC classification number: H01L25/18 ,  H01L25/0657 ,  H01L2225/06524 ,  H01L2225/06548

    Abstract: A fan-out type semiconductor package may include a frame, an upper chip stack, a first redistribution pattern, a lower chip stack, a second redistribution pattern and a redistribution post. The frame may have a cavity. The upper chip stack may be arranged in the cavity. The first redistribution pattern may be arranged under the frame. The first redistribution pattern may be electrically connected with the upper chip stack. The lower chip stack may be arranged under the first redistribution pattern. The second redistribution pattern may be arranged under the lower chip stack. The second redistribution pattern may be electrically connected with the lower chip stack. The redistribution post may be electrically connected between the first redistribution pattern and the second redistribution pattern. Thus, the fan-out type semiconductor package may have an improved heat dissipation characteristic with a thin thickness.

    SEMICONDUCTOR PACKAGE
    10.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20230075027A1

    公开(公告)日：2023-03-09

    申请号：US18055805

    申请日：2022-11-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Myungsam Kang ,  Yongjin Park ,  Youngchan Ko

    IPC: H01L21/56 ,  H01L23/00 ,  H01L23/367 ,  H01L23/552 ,  H01L25/16

    Abstract: A semiconductor package includes an interconnect structure having a first surface and a second surface opposing the first surface, and including a redistribution pattern and a vertical connection conductor, a first semiconductor chip disposed for a first inactive surface to oppose the first surface, a second semiconductor chip disposed on the first surface of the interconnect structure and disposed for the second inactive surface to oppose the first surface; a first encapsulant encapsulating the first and second semiconductor chips, a backside wiring layer disposed on the first encapsulant, a wiring structure connecting the redistribution pattern to the backside wiring layer, a heat dissipation member disposed on the second surface and connected to the vertical connection conductor.

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