公开(公告)号：US20140370704A1

公开(公告)日：2014-12-18

申请号：US14291670

申请日：2014-05-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Hoon AHN ,  Seung-Hyuk CHOI ,  Kyu-Hee HAN

IPC: H01L21/02 ,  H01L21/768

CPC classification number: H01L21/02203 ,  H01L21/02126 ,  H01L21/02208 ,  H01L21/02274 ,  H01L21/02348 ,  H01L21/7682 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming a dielectric layer are provided. The methods may include introducing oxygen radicals and organic silicon precursors into a chamber to form a preliminary dielectric layer on a substrate. Each of the organic silicon precursors may include a carbon bridge and a porogen such that the preliminary dielectric layer may include carbon bridges and porogens. The methods may also include removing at least some of the porogens from the preliminary dielectric layer to form a porous dielectric layer including the carbon bridges.

Abstract translation: 提供形成电介质层的方法。 所述方法可以包括将氧自由基和有机硅前体引入室中以在基底上形成预备介电层。 每个有机硅前体可以包括碳桥和致孔剂，使得预备介电层可以包括碳桥和致孔剂。 所述方法还可以包括从预备介电层中去除至少一些致孔剂以形成包括碳桥的多孔介电层。

公开(公告)号：US20200098620A1

公开(公告)日：2020-03-26

申请号：US16411439

申请日：2019-05-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woojin LEE ,  Hoon Seok SEO ,  Sanghoon AHN ,  Kyu-Hee HAN

IPC: H01L21/768 ,  H01L21/311

Abstract: A semiconductor device includes a substrate including an active pattern, a first interlayer dielectric layer on the substrate, the first interlayer dielectric layer including a recess on an upper portion thereof, and a lower connection line in the first interlayer dielectric layer, the lower connection line being electrically connected to the active pattern, and the lower connection line including a conductive pattern, the recess of the first interlayer dielectric layer selectively exposing a top surface of the conductive pattern, and a barrier pattern between the conductive pattern and the first interlayer dielectric layer, the first interlayer dielectric layer covering a top surface of the barrier pattern.

公开(公告)号：US20220285207A1

公开(公告)日：2022-09-08

申请号：US17826366

申请日：2022-05-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Jin KANG ,  Jong Min BAEK ,  Woo Kyung YOU ,  Kyu-Hee HAN ,  Han Seong KIM ,  Jang Ho LEE ,  Sang Shin JANG

IPC: H01L21/768 ,  H01L23/48

Abstract: A semiconductor device including a first interlayer insulating film; a conductive pattern in the first interlayer insulating film; a resistance pattern on the conductive pattern; an upper etching stopper film spaced apart from the resistance pattern, extending in parallel with a top surface of the resistance pattern, and including a first metal; a lower etching stopper film on the conductive pattern, extending in parallel with a top surface of the first interlayer insulating film, and including a second metal; and a second interlayer insulating film on the upper etching stopper film and the lower etching stopper film, wherein a distance from a top surface of the second interlayer insulating film to a top surface of the upper etching stopper film is smaller than a distance from the top surface of the second interlayer insulating film to a top surface of the lower etching stopper film.

公开(公告)号：US20210005551A1

公开(公告)日：2021-01-07

申请号：US16793366

申请日：2020-02-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jangho LEE ,  Jongmin Baek ,  Wookyung YOU ,  Kyu-Hee HAN ,  Suhyun Bark

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522

Abstract: Disclosed is a semiconductor device comprising a substrate, a first dielectric layer on the substrate, a first lower conductive line in the first dielectric layer, an etch stop layer on the first dielectric layer, a via-structure that penetrates the etch stop layer and connects to the first lower conductive line, a second dielectric layer on the etch stop layer, and an upper conductive line that penetrates the second dielectric layer and connects to the via-structure. The first dielectric layer includes a dielectric pattern at a level higher than a top surface of the first lower conductive line. The upper conductive line is in contact with a top surface of the etch stop layer. The etch stop layer has at an upper portion a rounded surface in contact with the via-structure.

公开(公告)号：US20180130697A1

公开(公告)日：2018-05-10

申请号：US15616334

申请日：2017-06-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Shin JANG ,  Woo-Kyung YOU ,  Kyu-Hee HAN ,  Jong-Min BAEK ,  Viet Ha NGUYEN ,  Byung-Hee KIM

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295

Abstract: A semiconductor device includes a first insulating interlayer on a first region of a substrate and a second insulating interlayer on a second region of the substrate, a plurality of first wiring structures on the first insulating interlayer, the first wiring structures being spaced apart from each other, a plurality of second wiring structures filling a plurality of trenches on the second insulating interlayer, respectively, an insulation capping structure selectively on a surface of the first insulating interlayer between the first wiring structures and on a sidewall and an upper surface of each of the first wiring structures, the insulation capping structure including an insulating material, a third insulating interlayer on the first and second wiring structures, and an air gap among the first wiring structures under the third insulating interlayer.

公开(公告)号：US20240087956A1

公开(公告)日：2024-03-14

申请号：US18510732

申请日：2023-11-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woojin LEE ,  Hoon Seok SEO ,  Sanghoon AHN ,  Kyu-Hee HAN

IPC: H01L21/768 ,  H01L23/528

CPC classification number: H01L21/76897 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76883 ,  H01L21/76885 ,  H01L23/5283

Abstract: A semiconductor device includes a substrate including an active pattern, a first interlayer dielectric layer on the substrate, the first interlayer dielectric layer including a recess on an upper portion thereof, and a lower connection line in the first interlayer dielectric layer, the lower connection line being electrically connected to the active pattern, and the lower connection line including a conductive pattern, the recess of the first interlayer dielectric layer selectively exposing a top surface of the conductive pattern, and a barrier pattern between the conductive pattern and the first interlayer dielectric layer, the first interlayer dielectric layer covering a top surface of the barrier pattern.

公开(公告)号：US20230411498A1

公开(公告)日：2023-12-21

申请号：US18175821

申请日：2023-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyu-Hee HAN ,  Bong Kwan BAEK ,  Sang Shin JANG ,  Koung Min RYU ,  Jong Min BAEK ,  Jung Hoo SHIN ,  Jun Hyuk LIM ,  Jung Hwan CHUN

IPC: H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/66795 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475

Abstract: A method for fabricating semiconductor device may include forming a source/drain pattern on a fin-type pattern, forming an etch stop film and an interlayer insulating film on the source/drain pattern, forming a contact hole in the interlayer insulating film, forming a sacrificial liner along a sidewall and a bottom surface of the contact hole, performing an ion implantation process while the sacrificial liner is present, removing the sacrificial liner and forming a contact liner along the sidewall of the contact hole, and forming a source/drain contact on the contact liner. The ion implantation process may include implant impurities into the source/drain pattern. The source/drain contact may be connected to the source/drain pattern.

公开(公告)号：US20230114920A1

公开(公告)日：2023-04-13

申请号：US18079998

申请日：2022-12-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woojin LEE ,  Hoon Seok SEO ,  Sanghoon AHN ,  Kyu-Hee HAN

IPC: H01L21/768 ,  H01L23/528

Abstract: A semiconductor device includes a substrate including an active pattern, a first interlayer dielectric layer on the substrate, the first interlayer dielectric layer including a recess on an upper portion thereof, and a lower connection line in the first interlayer dielectric layer, the lower connection line being electrically connected to the active pattern, and the lower connection line including a conductive pattern, the recess of the first interlayer dielectric layer selectively exposing a top surface of the conductive pattern, and a barrier pattern between the conductive pattern and the first interlayer dielectric layer, the first interlayer dielectric layer covering a top surface of the barrier pattern.

公开(公告)号：US20220005763A1

公开(公告)日：2022-01-06

申请号：US17480615

申请日：2021-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jangho LEE ,  Jongmin BAEK ,  Wookyung YOU ,  Kyu-Hee HAN ,  Suhyun BARK

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522

Abstract: Disclosed is a semiconductor device comprising a substrate, a first dielectric layer on the substrate, a first lower conductive line in the first dielectric layer, an etch stop layer on the first dielectric layer, a via-structure that penetrates the etch stop layer and connects to the first lower conductive line, a second dielectric layer on the etch stop layer, and an upper conductive line that penetrates the second dielectric layer and connects to the via-structure. The first dielectric layer includes a dielectric pattern at a level higher than a top surface of the first lower conductive line. The upper conductive line is in contact with a top surface of the etch stop layer. The etch stop layer has at an upper portion a rounded surface in contact with the via-structure.

公开(公告)号：US20210166974A1

公开(公告)日：2021-06-03

申请号：US17174409

申请日：2021-02-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woojin LEE ,  Hoon Seok SEO ,  Sanghoon AHN ,  Kyu-Hee HAN

IPC: H01L21/768 ,  H01L23/528

Abstract: A semiconductor device includes a substrate including an active pattern, a first interlayer dielectric layer on the substrate, the first interlayer dielectric layer including a recess on an upper portion thereof, and a lower connection line in the first interlayer dielectric layer, the lower connection line being electrically connected to the active pattern, and the lower connection line including a conductive pattern, the recess of the first interlayer dielectric layer selectively exposing a top surface of the conductive pattern, and a barrier pattern between the conductive pattern and the first interlayer dielectric layer, the first interlayer dielectric layer covering a top surface of the barrier pattern.