公开(公告)号：US20170358665A1

公开(公告)日：2017-12-14

申请号：US15361110

申请日：2016-11-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEUNG MIN SONG ,  DONG CHAN SUH ,  JUNG GIL YANG ,  GEUM JONG BAE ,  WOO BIN SONG

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L29/66795 ,  H01L29/0676 ,  H01L29/4236 ,  H01L29/42392 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66666 ,  H01L29/78696

Abstract: A method of manufacturing semiconductor device includes forming a plurality of sacrificial layers and a plurality of semiconductor layers repeatedly and alternately stacked on a substrate, partially removing the sacrificial layers, forming spacers in removed regions of the sacrificial layers, and replacing remaining portions of the sacrificial layers with a gate electrode. Each of the sacrificial layers includes first portions disposed adjacent to the plurality of semiconductor layers and a second portions disposed between the first portions. The second portion having a different composition from the first portions.

公开(公告)号：US20230081793A1

公开(公告)日：2023-03-16

申请号：US18056954

申请日：2022-11-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： WOO BIN SONG ,  SANG WOO LEE ,  MIN HEE CHO

IPC: H01L29/08 ,  H01L29/51 ,  H01L29/417 ,  H01L29/45 ,  H01L29/24 ,  H01L29/786 ,  H01L29/267

Abstract: Aspects of the present inventive concept provide a semiconductor device capable of enhancing performance and reliability through source/drain engineering in a transistor including an oxide semiconductor layer. The semiconductor device includes a substrate, a metal oxide layer disposed on the substrate, a source/drain pattern being in contact with the metal oxide layer and including a portion protruding from a top surface of the metal oxide layer, a plurality of gate structures disposed on the metal oxide layer with the source/drain pattern interposed therebetween and each including gate spacers and an insulating material layer, the insulating material layer being in contact with the metal oxide layer, and not extending along a top surface of the source/drain pattern, and a contact disposed on the source/drain pattern, the contact being connected to the source/drain pattern.

公开(公告)号：US20180122922A1

公开(公告)日：2018-05-03

申请号：US15800242

申请日：2017-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： SEOKHOON KIM ,  WOO BIN SONG ,  SUNJUNG KIM ,  JinBum KIM ,  SANGMOON LEE ,  SEUNG HUN LEE ,  DONGSUK SHIN

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L21/762 ,  H01L23/31

CPC classification number: H01L29/66795 ,  H01L21/76224 ,  H01L23/3171 ,  H01L29/16 ,  H01L29/20 ,  H01L29/267 ,  H01L29/42364 ,  H01L29/785 ,  H01L29/7851

Abstract: Disclosed is a semiconductor device. The semiconductor device comprises a fin structure on a substrate, device isolation patterns provided on the substrate and disposed on opposite sides of the fin structure, a gate electrode running across the fin structure and the device isolation patterns, a gate dielectric pattern between the gate electrode and the fin structure and between the gate electrode and the device isolation patterns, and a capping layer between the substrate and the device isolation patterns and between the fin structure and the device isolation patterns. The capping layer has a thickness greater than a thickness of the gate dielectric pattern.

公开(公告)号：US20240204068A1

公开(公告)日：2024-06-20

申请号：US18224864

申请日：2023-07-21

Applicant: Samsung electronics Co., Ltd.

Inventor： HYUNGJOO NA ,  WOO BIN SONG ,  JIN-WOOK YANG ,  Cheoljin YUN ,  YOSHINAO HARADA

IPC: H01L29/417 ,  H01L23/48 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/41775 ,  H01L23/481 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/495 ,  H01L29/4975 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes a substrate including an active pattern, a channel pattern on the active pattern, the channel pattern including a plurality of semiconductor patterns that are spaced apart from each other and are vertically stacked, a source/drain pattern connected to the plurality of semiconductor patterns, a through pattern penetrating the source/drain pattern, a metal-semiconductor compound layer between the source/drain pattern and the through pattern, a gate electrode on the plurality of semiconductor patterns, the gate electrode including inner electrodes between adjacent semiconductor patterns of the plurality of semiconductor patterns and an outer electrode on an uppermost semiconductor pattern of the plurality of semiconductor patterns, an active contact on the through pattern, and a first metal layer on the active contact, the first metal layer including a power wiring and first wirings connected to the active contact.

公开(公告)号：US20220246180A1

公开(公告)日：2022-08-04

申请号：US17481583

申请日：2021-09-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： WONSOK LEE ,  MIN TAE RYU ,  WOO BIN SONG ,  KISEOK LEE ,  MINSU LEE ,  MIN HEE CHO

IPC: G11C5/06 ,  H01L29/06 ,  H01L27/108

Abstract: A semiconductor memory includes a bit line extending in a first direction, first and second active patterns, which are alternately disposed in the first direction and on the bit line, and each of which includes a horizontal portion and a vertical portion, first word lines disposed on the horizontal portions of the first active patterns to cross the bit line, second word lines disposed on the horizontal portions of the second active patterns to cross the bit line, and an intermediate structure provided in a first gap region between the first and second word lines or in a second gap region between the vertical portions of the first and second active patterns. The first and second active patterns, which are adjacent to each other, may be disposed to be symmetric with respect to each other.

公开(公告)号：US20220013525A1

公开(公告)日：2022-01-13

申请号：US17172124

申请日：2021-02-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： MIN HEE CHO ,  HYUNMOG PARK ,  WOO BIN SONG ,  MINSU LEE ,  WONSOK LEE

IPC: H01L27/108

Abstract: A semiconductor memory device is provided. The device may include a lower gate line provided on a substrate and extended in a first direction, an upper gate line vertically overlapped with the lower gate line and extended in the first direction, a first capacitor provided between the lower gate line and the upper gate line, a second capacitor provided between the lower gate line and the upper gate line and spaced apart from the first capacitor in the first direction, a lower semiconductor pattern provided to penetrate the lower gate line and connected to the first capacitor, an upper semiconductor pattern provided to penetrate the upper gate line and connected to the second capacitor, and a lower insulating pattern provided between the second capacitor and the lower gate line to cover the entire region of a bottom surface of the second capacitor.