公开(公告)号：US10438671B1

公开(公告)日：2019-10-08

申请号：US16015612

申请日：2018-06-22

Applicant: SanDisk Technologies LLC

Inventor： Hong-Yan Chen ,  Yingda Dong

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C11/56

Abstract: Techniques for reducing program disturb of memory cells which are formed in a two-tier stack, when a selected word line is in the upper tier. In one approach, at the start of the program phase of a program loop, voltages of word lines adjacent to the interface are increased to a pass voltage before voltages of remaining word lines are increased to a pass voltage. This delay provides time for residue electrons in the lower tier to move toward the drain end of a NAND string to reduce the likelihood of program disturb. In another approach, the voltages of the word lines adjacent to the interface are maintained at 0 V or other turn-off voltage during the program phase to block the passage of residue electrons from the lower tier to the upper tier.

公开(公告)号：US20190074062A1

公开(公告)日：2019-03-07

申请号：US15694008

申请日：2017-09-01

Applicant: SanDisk Technologies LLC

Inventor： Hong-Yan Chen ,  Wei Zhao ,  Ching-Huang Lu ,  Yingda Dong

IPC: G11C16/08 ,  G11C16/04

Abstract: A memory device and associated techniques for reducing read disturb of memory cells during a sensing process. Select gate transistors are transitioned to a conductive state one or more time during a sensing process, at the drain and/or source ends of the memory strings in an unselected sub-block. The transitioning can occur periodically, multiple times during the sensing process. When the select gate transistors are in a conductive state, accumulated holes in the channel can be removed. This help provide a faster decrease of the channel potential when the unselected word line voltages are ramped down at the end of the sensing process. The duration of a disturb-inducing channel gradient which is created next to the edge data memory cell is reduced so that read disturb of this cell is also reduced.

公开(公告)号：US20190355429A1

公开(公告)日：2019-11-21

申请号：US15983365

申请日：2018-05-18

Applicant: SanDisk Technologies LLC

Inventor： Hong-Yan Chen ,  Yingda Dong

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/30 ,  G11C16/04 ,  H01L29/788 ,  H01L27/11524

Abstract: Apparatuses and techniques are described for reducing an injection type of program disturb in a memory device. A voltage on a selected word line is increased in a first step from an initial level such as 0 V to an intermediate, pass level such as Vpass, and in a second step from Vpass to a peak program level of Vpgm. A voltage on an adjacent unselected word line can be increased from the initial level to Vpass and then temporarily increased to an elevated level of Vpass_el during the second step increase on the selected word line. This helps reduce the magnitude of a channel gradient between the selected word line and the adjacent word line. The increase to Vpass_el may be implemented for program loops in the later part of a program operation, when Vpgm and the risk of program disturb is relatively high.

公开(公告)号：US10026487B2

公开(公告)日：2018-07-17

申请号：US15172653

申请日：2016-06-03

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hong-Yan Chen ,  Yingda Dong

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/16

Abstract: A non-volatile memory system includes one or more control circuits configured to program memory cells and verify the programming. The verifying of the programmed memory cells includes applying one or more voltages to perform boosting of a channel region associated with unselected memory cells, allowing the boosting of the channel region for a portion of time while applying the one or more voltages, preventing/interrupting the boosting of the channel region while applying the one or more voltages for a duration of time based on position of a memory cell selected for verification, applying a compare signal to the memory cell selected for verification, and performing a sensing operation for the memory cell selected for verification in response to the compare signal.

公开(公告)号：US09905305B2

公开(公告)日：2018-02-27

申请号：US15208843

申请日：2016-07-13

Applicant: SanDisk Technologies LLC

Inventor： Hong-Yan Chen ,  Yingda Dong

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/26 ,  G11C11/56 ,  G11C16/08 ,  G11C16/32 ,  G11C11/04

CPC classification number: G11C16/3427 ,  G11C11/04 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3459

Abstract: Read disturb due to hot electron injection is reduced in a 3D memory device by controlling the magnitude and timing of word line and select gate ramp down voltages at the end of a sensing operation. In an example read operation, a predefined subset of word lines includes source-side and drain-side word lines. For the predefined subset of word lines, word line voltages are ramped down before the voltages of the select gates are ramped down. Subsequently, for a remaining subset of word lines, word line voltages are ramped down, but no later than the ramping down of the voltages of the select gates. The timing of the ramp down of the selected word line depends on whether it is among the predefined subset or the remaining subset. The predefined subset can include a number of adjacent or non-adjacent word lines.

公开(公告)号：US10770157B1

公开(公告)日：2020-09-08

申请号：US16418642

申请日：2019-05-21

Applicant: SanDisk Technologies LLC

Inventor： Hong-Yan Chen ,  Wei Zhao ,  Henry Chin

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/10

Abstract: Techniques are described for reducing an injection type of program disturb in a memory device during the pre-charge phase of a program loop. In one approach, a pre-charge voltage on the selected word line and drain side word lines is adjusted based on a risk of the injection type of program disturb. Risk factors such as temperature, WLn position, Vpgm and the selected sub-block, can be used to set the pre-charge voltage to be lower when the risk is higher. In another approach, the pre-charge voltage on the source side word lines is adjusted to reduce a channel gradient and/or the amount of time in which the injection type of program disturb occurs.

公开(公告)号：US10748627B2

公开(公告)日：2020-08-18

申请号：US16229639

申请日：2018-12-21

Applicant: SanDisk Technologies LLC

Inventor： Hong-Yan Chen ,  Yingda Dong ,  Zhengyi Zhang

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/10 ,  G11C11/56 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11556

Abstract: Techniques for reducing neighbor word line interference (NWI) of memory cells which are formed in a two-tier stack having a lower tier and an upper tier separated by an interface. In one approach, an upward word line programming order is used for a top portion of the top tier, and a downward word line programming order is used for a bottom portion of the top tier and for the bottom tier. Additionally, for memory cells which receive NWI from both adjacent word lines, options include programming fewer bits per cell, performing multi-pass programming and/or use lower verify voltages. Options also include increasing a control gate length of the memory cells and increasing a height of a dielectric region adjacent to the memory cells.

公开(公告)号：US10249372B2

公开(公告)日：2019-04-02

申请号：US15694008

申请日：2017-09-01

Applicant: SanDisk Technologies LLC

Inventor： Hong-Yan Chen ,  Wei Zhao ,  Ching-Huang Lu ,  Yingda Dong

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16

Abstract: A memory device and associated techniques for reducing read disturb of memory cells during a sensing process. Select gate transistors are transitioned to a conductive state one or more time during a sensing process, at the drain and/or source ends of the memory strings in an unselected sub-block. The transitioning can occur periodically, multiple times during the sensing process. When the select gate transistors are in a conductive state, accumulated holes in the channel can be removed. This help provide a faster decrease of the channel potential when the unselected word line voltages are ramped down at the end of the sensing process. The duration of a disturb-inducing channel gradient which is created next to the edge data memory cell is reduced so that read disturb of this cell is also reduced.

公开(公告)号：US20190057749A1

公开(公告)日：2019-02-21

申请号：US15678683

申请日：2017-08-16

Applicant: SanDisk Technologies LLC

Inventor： Hong-Yan Chen ,  Yingda Dong

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/28 ,  G11C16/04

Abstract: A memory device and associated techniques for reducing read disturb of memory cells during a sensing process. The drain-end select gate transistors of unselected sub-blocks are made temporarily conductive for a time period during the ramp up of the unselected word line voltages to reduce the amount of capacitive coupling up of the respective memory string channel. This reduces a channel gradient which can exist in the memory string channels, thereby also reducing the read disturb. Further, the time period is greater when the selected word line is in a source-end or midrange subset of the word lines than when the selected word line is in a drain-end subset of the word lines. Another option involves omitting the injection disturb countermeasure, or providing a less severe injection disturb countermeasure, when the unselected sub-blocks are unprogrammed.

公开(公告)号：US20180308556A1

公开(公告)日：2018-10-25

申请号：US15495178

申请日：2017-04-24

Applicant: SanDisk Technologies LLC

Inventor： Ashish Baraskar ,  Liang Pang ,  Yingda Dong ,  Ching-Huang Lu ,  Nan Lu ,  Hong-Yan Chen

IPC: G11C16/34 ,  G11C16/28 ,  G11C16/16 ,  G11C16/04 ,  G11C16/32 ,  G11C16/08

CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/16 ,  G11C16/28 ,  G11C16/32 ,  G11C16/3459

Abstract: A memory device and associated techniques to reduce charge loss of memory cells. In one aspect, a charge loss countermeasure is performed if a word line selected for programming is adjacent to a dummy word line. The countermeasure can involve programming the dummy memory cells through injection disturb. In one approach, the timing is adjusted for the voltages on the selected word line and the dummy word line at the end of a program voltage. The selected word line voltage can be decreased more quickly, or the dummy word line voltage can be decreased more slowly. The decrease of the dummy word line voltage can also be delayed. Another approach involves elevating the bit line voltage during the decrease of the selected word line voltage. The bit line voltage can be a function of the assigned data state of a selected cell.