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    SYSTEMS AND METHODS FOR HIGH-PERFORMANCE WRITE OPERATIONS
    5.
    发明申请
    SYSTEMS AND METHODS FOR HIGH-PERFORMANCE WRITE OPERATIONS 审中-公开

    公开(公告)号：US20190180831A1

    公开(公告)日：2019-06-13

    申请号：US15967572

    申请日：2018-04-30

    Applicant: SanDisk Technologies LLC

    Inventor： Pitamber Shukla ,  Mohan Dunga ,  Anubhav Khandelwal

    IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/04 ,  G11C11/4074 ,  G11C29/52 ,  G06F3/06

    Abstract: A high-performance write operation to program data to a group of non-volatile memory cells may be completed in response to applying a single programming pulse to the group. Programming of the cells may be verified (and/or corrected) after completion of the command. Verifying programming of the cells may comprise identifying under-programmed cells, and applying an additional programming pulse to the identified cells. The under-programmed cells may comprise cells within an under-program range below a target level. The under-program range may be determined based on a threshold voltage distribution of the cells in response to applying the single programming pulse.

    System and method for programming non-volatile memory during burst sequential write
    6.
    发明授权
    System and method for programming non-volatile memory during burst sequential write 有权

    公开(公告)号：US10714169B1

    公开(公告)日：2020-07-14

    申请号：US16437355

    申请日：2019-06-11

    Applicant: SanDisk Technologies LLC

    Inventor： Phil Reusswig ,  Pitamber Shukla ,  Sarath Puthenthermadam ,  Mohan Dunga ,  Sahil Sharma ,  Rohit Sehgal ,  Niles Yang

    IPC: G11C11/56 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/04

    Abstract: A non-volatile memory system and corresponding method of operation are provided. The system includes non-volatile memory cells, each retaining a threshold voltage within a threshold window. The non-volatile memory cells include multi-bit cells each configured to store a plurality of bits of data with the threshold window partitioned into bands each having a band width. The bands include a lowest band denoting an erased state and increasing bands. A control circuit programs a first set of the data into the multi-bit cells in a single-bit mode using first target states being one of the erased state and a tight intermediate state having a distribution of the threshold voltage no wider than the band width of one of the increasing bands. The control circuit also programs a second set of the data into the multi-bit cells in a multi-bit mode with each of the multi-bit cells storing the plurality of bits.

    Adaptive hard and soft bit decoding
    7.
    发明授权
    Adaptive hard and soft bit decoding 有权

    公开(公告)号：US10025661B1

    公开(公告)日：2018-07-17

    申请号：US15391455

    申请日：2016-12-27

    Applicant: SanDisk Technologies LLC

    Inventor： Pitamber Shukla ,  Joanna Lai ,  Henry Chin ,  Deepak Raghu ,  Abhilash Kashyap

    IPC: G06F11/00 ,  G06F11/10 ,  G11C29/52 ,  G11C16/34 ,  G11C16/28 ,  G11C16/10

    Abstract: Technology is described herein for operating non-volatile storage. In one embodiment, the memory system tracks which adjustments to default values for hard bit read reference voltages are most frequently successful to decode data in non-volatile memory cells. In response to a process that uses only hard bits failing to successfully decode data in a group of the non-volatile memory cells, the memory system attempts to decode the data in the group of non-volatile memory cells using dynamic hard bit read reference voltages and dynamic soft bit read reference voltages that correspond to only a subset of the most frequently successful adjustments to the default values for the hard bit read reference voltages. By only using a subset of the most frequently successful adjustments to the default values for the hard bit read reference voltages time and power is saved.

    SYSTEMS AND METHODS FOR HIGH-PERFORMANCE WRITE OPERATIONS
    8.
    发明申请
    SYSTEMS AND METHODS FOR HIGH-PERFORMANCE WRITE OPERATIONS 审中-公开

    公开(公告)号：US20200035313A1

    公开(公告)日：2020-01-30

    申请号：US16591210

    申请日：2019-10-02

    Applicant: Sandisk Technologies LLC

    Inventor： Pitamber Shukla ,  Mohan Dunga ,  Anubhav Khandelwal

    IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G06F3/06 ,  G11C11/4074 ,  G11C29/52

    Abstract: A high-performance write operation to program data to a group of non-volatile memory cells may be completed in response to applying a single programming pulse to the group. Programming of the cells may be verified (and/or corrected) after completion of the command. Verifying programming of the cells may comprise identifying under-programmed cells, and applying an additional programming pulse to the identified cells. The under-programmed cells may comprise cells within an under-program range below a target level. The under-program range may be determined based on a threshold voltage distribution of the cells in response to applying the single programming pulse.

    NON-VOLATILE MEMORY WITH FAST PARTIAL PAGE OPERATION
    9.
    发明申请
    NON-VOLATILE MEMORY WITH FAST PARTIAL PAGE OPERATION 审中-公开

    公开(公告)号：US20190180822A1

    公开(公告)日：2019-06-13

    申请号：US15955156

    申请日：2018-04-17

    Applicant: SanDisk Technologies LLC

    Inventor： Mohan V Dunga ,  Pitamber Shukla

    IPC: G11C16/10 ,  G11C13/00 ,  G11C16/04 ,  G11C16/08 ,  G11C16/34 ,  G11C16/26

    Abstract: A non-volatile memory system comprises a memory structure and a control circuit connected to the memory structure. The memory structure includes one or more planes of non-volatile memory cells. Each plane is divided into a plurality of partial planes. The control circuit is configured to write to and read from the memory cells by writing a partial page into a particular partial plane and reading the partial page from the particular partial plane using a set of parameters optimized for the particular partial plane.

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