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公开(公告)号：US11081187B2
公开(公告)日：2021-08-03
申请号：US16710526
申请日：2019-12-11
Applicant: SanDisk Technologies LLC
Inventor： Sahil Sharma , Phil Reusswig , Rohit Sehgal , Piyush A. Dhotre , Niles Yang
Abstract: A method of operating a storage device, including; performing, by a non-volatile memory, an erase operation on a block of memory in the non-volatile memory, where the non-volatile memory is coupled to a controller; receiving, by the non-volatile memory, a host-transaction within a first time period, where, the non-volatile memory is coupled to a host device; and suspending, by the non-volatile memory, an erase operation in response to receiving the host-transaction by: determining the erase operation has completed a charge phase; and suspending the erase operation during a pulse phase of the erase operation. The method additionally includes the non-volatile memory maintaining a loop counter and a pulse counter, where: the loop counter increments in response to completion of an erase loop, and the pulse counter increments in response to completion of an erase pulse, where the erase pulse is applied during a pulse phase of the erase operation.
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Patent Agency Ranking
公开(公告)号：US10714169B1
公开(公告)日：2020-07-14
申请号：US16437355
申请日：2019-06-11
Applicant: SanDisk Technologies LLC
Inventor： Phil Reusswig , Pitamber Shukla , Sarath Puthenthermadam , Mohan Dunga , Sahil Sharma , Rohit Sehgal , Niles Yang
Abstract: A non-volatile memory system and corresponding method of operation are provided. The system includes non-volatile memory cells, each retaining a threshold voltage within a threshold window. The non-volatile memory cells include multi-bit cells each configured to store a plurality of bits of data with the threshold window partitioned into bands each having a band width. The bands include a lowest band denoting an erased state and increasing bands. A control circuit programs a first set of the data into the multi-bit cells in a single-bit mode using first target states being one of the erased state and a tight intermediate state having a distribution of the threshold voltage no wider than the band width of one of the increasing bands. The control circuit also programs a second set of the data into the multi-bit cells in a multi-bit mode with each of the multi-bit cells storing the plurality of bits.
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公开(公告)号：US10248499B2
公开(公告)日：2019-04-02
申请号：US15192901
申请日：2016-06-24
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Rohit Sehgal , Nian Niles Yang
Abstract: A first phase of a programming process is performed to program data into a set of non-volatile memory cells using a set of verify references and allowing for a first number of programming errors. After completing the first phase of programming, an acknowledgement is provided to the host that the programming was successful. The memory system reads the data from the set of non-volatile memory cells and uses an error correction process to identify and correct error bits in the data read. When the memory system is idle and after the acknowledgement is provided to the host, the memory system performs a second phase of the programming process to program the corrected error bits into the set of the non-volatile memory cells using the same set of verify references and allowing for a second number of programming errors.
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公开(公告)号：US20170371744A1
公开(公告)日：2017-12-28
申请号：US15192901
申请日：2016-06-24
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Rohit Sehgal , Nian Niles Yang
CPC classification number: G06F11/1068 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C29/42 , G11C29/44 , G11C29/52
Abstract: A first phase of a programming process is performed to program data into a set of non-volatile memory cells using a set of verify references and allowing for a first number of programming errors. After completing the first phase of programming, an acknowledgement is provided to the host that the programming was successful. The memory system reads the data from the set of non-volatile memory cells and uses an error correction process to identify and correct error bits in the data read. When the memory system is idle and after the acknowledgement is provided to the host, the memory system performs a second phase of the programming process to program the corrected error bits into the set of the non-volatile memory cells using the same set of verify references and allowing for a second number of programming errors.
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公开(公告)号：US20210183450A1
公开(公告)日：2021-06-17
申请号：US16710526
申请日：2019-12-11
Applicant: SanDisk Technologies LLC
Inventor： Sahil Sharma , Phil Reusswig , Rohit Sehgal , Piyush A. Dhotre , Niles Yang
Abstract: A method of operating a storage device, including; performing, by a non-volatile memory, an erase operation on a block of memory in the non-volatile memory, where the non-volatile memory is coupled to a controller; receiving, by the non-volatile memory, a host-transaction within a first time period, where, the non-volatile memory is coupled to a host device; and suspending, by the non-volatile memory, an erase operation in response to receiving the host-transaction by: determining the erase operation has completed a charge phase; and suspending the erase operation during a pulse phase of the erase operation. The method additionally includes the non-volatile memory maintaining a loop counter and a pulse counter, where: the loop counter increments in response to completion of an erase loop, and the pulse counter increments in response to completion of an erase pulse, where the erase pulse is applied during a pulse phase of the erase operation.
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公开(公告)号：US09934858B2
公开(公告)日：2018-04-03
申请号：US14700500
申请日：2015-04-30
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Niles Yang , Rohit Sehgal , Abhilash Kashyap
CPC classification number: G11C16/10 , G11C7/14 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C16/26 , G11C16/28 , G11C2211/5641 , G11C2211/5646
Abstract: In a non-volatile memories formed according to a NAND type of architecture, one or more of the end word lines on the source end, drain end, or both are set aside as dummy word lines that are not used to store user data. In addition to the host data, a memory system typically also stores metadata, or information about the user data, how it is stored and the memory system itself. Techniques are presented for using the dummy word lines of the memory blocks to hold this metadata. This arrangement allows for the metadata of a memory block to be known in real time, without reducing the storage capacity of the memory system.
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