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    Detection of a last programming loop for system performance gain
    2.
    发明授权
    Detection of a last programming loop for system performance gain 有权

    公开(公告)号：US11211132B2

    公开(公告)日：2021-12-28

    申请号：US16803366

    申请日：2020-02-27

    Applicant: SanDisk Technologies LLC

    Inventor： Piyush A. Dhotre ,  Sahil Sharma ,  Niles Yang ,  Phil Reusswig

    IPC: G11C16/04 ,  G11C16/34 ,  G11C16/10 ,  G06F9/54 ,  G06F9/30 ,  G11C16/26

    Abstract: A memory apparatus and method of operation is provided. The apparatus includes a plurality of memory cells coupled to a control circuit. The control circuit is configured to receive data indicating a data state for each memory cell of a set of memory cells of the plurality of memory cells and program, in multiple programming loops, the set of memory cells according to the data indicating the data state for each memory cell of the set of memory cells. The control circuit is further configured to determine that the programming of the set of memory cells is in a last programming loop of the multiple programming loops and in response to the determination, receive data indicating a data state for each memory cell of another set of memory cells of the plurality of memory cells.

    ERASE SUSPEND SCHEME IN A STORAGE DEVICE
    4.
    发明申请
    ERASE SUSPEND SCHEME IN A STORAGE DEVICE 有权

    公开(公告)号：US20210183450A1

    公开(公告)日：2021-06-17

    申请号：US16710526

    申请日：2019-12-11

    Applicant: SanDisk Technologies LLC

    Inventor： Sahil Sharma ,  Phil Reusswig ,  Rohit Sehgal ,  Piyush A. Dhotre ,  Niles Yang

    IPC: G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/08 ,  G11C16/34

    Abstract: A method of operating a storage device, including; performing, by a non-volatile memory, an erase operation on a block of memory in the non-volatile memory, where the non-volatile memory is coupled to a controller; receiving, by the non-volatile memory, a host-transaction within a first time period, where, the non-volatile memory is coupled to a host device; and suspending, by the non-volatile memory, an erase operation in response to receiving the host-transaction by: determining the erase operation has completed a charge phase; and suspending the erase operation during a pulse phase of the erase operation. The method additionally includes the non-volatile memory maintaining a loop counter and a pulse counter, where: the loop counter increments in response to completion of an erase loop, and the pulse counter increments in response to completion of an erase pulse, where the erase pulse is applied during a pulse phase of the erase operation.

    DETECTION OF A LAST PROGRAMMING LOOP FOR SYSTEM PERFORMANCE GAIN
    5.
    发明申请
    DETECTION OF A LAST PROGRAMMING LOOP FOR SYSTEM PERFORMANCE GAIN 有权

    公开(公告)号：US20210272639A1

    公开(公告)日：2021-09-02

    申请号：US16803366

    申请日：2020-02-27

    Applicant: SanDisk Technologies LLC

    Inventor： Piyush A. Dhotre ,  Sahil Sharma ,  Niles Yang ,  Phil Reusswig

    IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G06F9/30 ,  G06F9/54

    Abstract: A memory apparatus and method of operation is provided. The apparatus includes a plurality of memory cells coupled to a control circuit. The control circuit is configured to receive data indicating a data state for each memory cell of a set of memory cells of the plurality of memory cells and program, in multiple programming loops, the set of memory cells according to the data indicating the data state for each memory cell of the set of memory cells. The control circuit is further configured to determine that the programming of the set of memory cells is in a last programming loop of the multiple programming loops and in response to the determination, receive data indicating a data state for each memory cell of another set of memory cells of the plurality of memory cells.

    Erase suspend scheme in a storage device
    6.
    发明授权
    Erase suspend scheme in a storage device 有权

    公开(公告)号：US11081187B2

    公开(公告)日：2021-08-03

    申请号：US16710526

    申请日：2019-12-11

    Applicant: SanDisk Technologies LLC

    Inventor： Sahil Sharma ,  Phil Reusswig ,  Rohit Sehgal ,  Piyush A. Dhotre ,  Niles Yang

    IPC: G11C16/16 ,  G11C16/26 ,  G11C16/34 ,  G11C16/08 ,  G11C16/30

    Abstract: A method of operating a storage device, including; performing, by a non-volatile memory, an erase operation on a block of memory in the non-volatile memory, where the non-volatile memory is coupled to a controller; receiving, by the non-volatile memory, a host-transaction within a first time period, where, the non-volatile memory is coupled to a host device; and suspending, by the non-volatile memory, an erase operation in response to receiving the host-transaction by: determining the erase operation has completed a charge phase; and suspending the erase operation during a pulse phase of the erase operation. The method additionally includes the non-volatile memory maintaining a loop counter and a pulse counter, where: the loop counter increments in response to completion of an erase loop, and the pulse counter increments in response to completion of an erase pulse, where the erase pulse is applied during a pulse phase of the erase operation.

    System and method for programming non-volatile memory during burst sequential write
    7.
    发明授权
    System and method for programming non-volatile memory during burst sequential write 有权

    公开(公告)号：US10714169B1

    公开(公告)日：2020-07-14

    申请号：US16437355

    申请日：2019-06-11

    Applicant: SanDisk Technologies LLC

    Inventor： Phil Reusswig ,  Pitamber Shukla ,  Sarath Puthenthermadam ,  Mohan Dunga ,  Sahil Sharma ,  Rohit Sehgal ,  Niles Yang

    IPC: G11C11/56 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/04

    Abstract: A non-volatile memory system and corresponding method of operation are provided. The system includes non-volatile memory cells, each retaining a threshold voltage within a threshold window. The non-volatile memory cells include multi-bit cells each configured to store a plurality of bits of data with the threshold window partitioned into bands each having a band width. The bands include a lowest band denoting an erased state and increasing bands. A control circuit programs a first set of the data into the multi-bit cells in a single-bit mode using first target states being one of the erased state and a tight intermediate state having a distribution of the threshold voltage no wider than the band width of one of the increasing bands. The control circuit also programs a second set of the data into the multi-bit cells in a multi-bit mode with each of the multi-bit cells storing the plurality of bits.

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