公开(公告)号：US5698880A

公开(公告)日：1997-12-16

申请号：US539380

申请日：1995-10-05

申请人： Shigeki Takahashi ,  Mitsuhiro Kataoka ,  Tsuyoshi Yamamoto ,  Yuuichi Takeuchi ,  Norihito Tokura

发明人： Shigeki Takahashi ,  Mitsuhiro Kataoka ,  Tsuyoshi Yamamoto ,  Yuuichi Takeuchi ,  Norihito Tokura

IPC分类号： H01L21/336 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： Y02E10/50

摘要： A manufacturing method for a semiconductor device, which can attain a low ion voltage in a manufacturing method for a semiconductor device involving a process for forming a groove by etching prior to selective oxidation, selectively oxidizing a region including the groove and thereby making a channel part of the groove, is disclosed. A groove part is thermally oxidized by using a silicon nitride film as a mask. A LOCOS oxide film is formed by this thermal oxidation, and concurrently a U-groove is formed on the surface of an n.sup.- -type epitaxial layer eroded by the LOCOS oxide film, and the shape of the U-groove is fixed. A curve part formed during a chemical dry etching process remains as a curve part on the side surface of the U-groove. Then, an n.sup.+ -type source layer is formed by means of thermal diffusion to a junction thickness of 0.5 to 1 .mu.m, and a channel is set up as well. The junction depth obtained by this thermal diffusion is set up more deeply than the curve part which is formed during the above etching and remains on the side surface of the U-groove after the above selective thermal oxidation.

摘要翻译： 一种用于半导体器件的制造方法的半导体器件的制造方法，其包括在选择性氧化之前通过蚀刻形成沟槽的工艺的半导体器件的制造方法，选择性地氧化包括沟槽的区域，从而形成沟道部分 的凹槽。 通过使用氮化硅膜作为掩模将槽部热氧化。 通过该热氧化形成LOCOS氧化物膜，并且在由LOCOS氧化物膜侵蚀的n型外延层的表面上形成U形槽，并且U形槽的形状被固定。 在化学干蚀刻过程中形成的曲线部分在U形槽的侧表面上保持为曲线部分。 然后，通过热扩散形成0.5±1μm的结合厚度的n +型源极层，并且还设置沟道。 通过该热扩散获得的结深度比在上述蚀刻期间形成的曲线部分更深地设置，并且在上述选择性热氧化之后保留在U形槽的侧表面上。

公开(公告)号：US5780324A

公开(公告)日：1998-07-14

申请号：US605637

申请日：1996-02-22

申请人： Norihito Tokura ,  Shigeki Takahashi ,  Tsuyoshi Yamamoto ,  Mitsuhiro Kataoka ,  Kunihiko Hara

发明人： Norihito Tokura ,  Shigeki Takahashi ,  Tsuyoshi Yamamoto ,  Mitsuhiro Kataoka ,  Kunihiko Hara

IPC分类号： H01L21/336 ,  H01L29/04 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L21/332

CPC分类号： H01L29/7813 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/4236

摘要： A manufacturing method of a vertical DMOSFET having a concave channel structure, which does not permit the introduction of defects or contaminant into the channel part and which can make the shape of the groove uniform, is disclosed. On a surface of a (100)-oriented n.sup.- -on-n.sup.+ epitaxial wafer is formed an initial groove by chemical dry etching. The grooved surface is then oxidized by LOCOS technique to form a LOCOS oxide film, whereby the concave structure is formed on the epitaxial wafer. The concave width is set to be at least twice the concave depth, and the sidewall angle is set to be approximately 50.degree. to make the sidewall plane (111) of high channel mobility plane. Following this process, p-type and n-type impurities are diffused from the main surface using the LOCOS oxide film as a double diffusion mask to form a body region and a source region.

摘要翻译： 公开了一种具有凹槽结构的垂直DMOSFET的制造方法，其不允许将缺陷或污染物引入通道部分并且可以使凹槽的形状均匀。 在（100）取向的n-on + n外延晶片的表面上，通过化学干蚀刻形成初始槽。 然后通过LOCOS技术将开槽的表面氧化以形成LOCOS氧化物膜，由此在外延晶片上形成凹形结构。 凹形宽度被设定为凹入深度的至少两倍，并且将侧壁角度设定为大约50°以使高通道迁移面的侧壁平面（111）。 在该过程之后，使用LOCOS氧化物膜作为双扩散掩模，从主表面扩散p型和n型杂质，以形成体区和源区。

公开(公告)号：US6015737A

公开(公告)日：2000-01-18

申请号：US515176

申请日：1995-08-15

申请人： Norihito Tokura ,  Shigeki Takahashi ,  Tsuyoshi Yamamoto ,  Mitsuhiro Kataoka

发明人： Norihito Tokura ,  Shigeki Takahashi ,  Tsuyoshi Yamamoto ,  Mitsuhiro Kataoka

IPC分类号： H01L21/336 ,  H01L29/04 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/045 ,  H01L29/0696 ,  H01L29/7813 ,  H01L29/4236

摘要： A vertical type power MOSFET remarkably reduces its ON-resistance per area. A substantial groove formation in which a gate structure is constituted is performed beforehand utilizing the LOCOS method before the formation of a p-type base layer and an n.sup.+ -type source layer. The p-type base layer and the n.sup.+ -type source layer are then formed by double diffusion in a manner of self-alignment with respect to a LOCOS oxide film, simultaneously with which channels are set at sidewall portions of the LOCOS oxide film. Thereafter the LOCOS oxide film is removed to provide a U-groove so as to constitute the gate structure. Namely, the channels are set by the double diffusion of the manner of self-alignment with respect to the LOCOS oxide film, so that the channels, which are set at the sidewall portions at both sides of the groove, provide a structure of exact bilateral symmetry, there is no positional deviation of the U-groove with respect to the base layer end, and the length of the bottom face of the U-groove can be made minimally short. Therefore, the unit cell size is greatly reduced, and the ON-resistance per area is greatly decreased.

摘要翻译： 垂直型功率MOSFET可显着降低每个区域的导通电阻。 在形成p型基极层和n +型源极层之前，利用LOCOS方法预先利用构成栅极结构的实质的槽形成。 然后通过相对于LOCOS氧化物膜的自对准的双扩散形成p型基极层和n +型源极层，同时将通道设置在LOCOS氧化物膜的侧壁部分。 此后，去除LOCOS氧化物膜以提供U形槽以构成栅极结构。 即，通过相对于LOCOS氧化膜的自对准方式的双扩散来设定通道，使得设置在凹槽两侧的侧壁部分处的通道提供精确双边的结构 U形槽相对于基底层端部没有位置偏离，U槽的底面的长度最短。 因此，单元电池尺寸大大降低，并且每个面积的导通电阻大大降低。

公开(公告)号：US5776812A

公开(公告)日：1998-07-07

申请号：US413410

申请日：1995-03-30

申请人： Shigeki Takahashi ,  Mitsuhiro Kataoka ,  Tsuyoshi Yamamoto ,  Yuuchi Takeuchi ,  Norihito Tokura

发明人： Shigeki Takahashi ,  Mitsuhiro Kataoka ,  Tsuyoshi Yamamoto ,  Yuuchi Takeuchi ,  Norihito Tokura

IPC分类号： H01L21/336 ,  H01L29/04 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/0696 ,  H01L29/045 ,  H01L29/7813 ,  H01L29/4236

摘要： A manufacturing method of a MOSFET having a channel part on the side surface of a groove, which does not permit the introduction of defects or contaminant into the channel part and which can make the shape of the groove uniform. An n.sup.- -type epitaxial layer having a low impurity concentration is formed on a main surface of an n.sup.+ -type semiconductor substrate. This surface is specified as a main surface, and chemical dry etching is applied to a specified region of this main surface. A region including a surface generated by the chemical dry etching is selectively oxidized to form a selective oxide film to a specified thickness. Following this process, p-type and n-type impurities are doubly diffused from the main surface to define the length of the channel and form a base layer and a source layer. Furthermore, the n.sup.+ -type semiconductor substrate is specified as a drain layer. After the double diffusion, a gate electrode is formed through a gate oxide film and a source electrode and a drain electrode are formed.

摘要翻译： 一种MOSFET的制造方法，其具有在槽的侧面上的通道部分，其不允许将缺陷或污染物引入通道部分中并且可以使槽的形状均匀。 在n +型半导体衬底的主表面上形成具有低杂质浓度的n型外延层。 该表面被指定为主表面，并且化学干蚀刻被施加到该主表面的指定区域。 包括通过化学干蚀刻生成的表面的区域被选择性地氧化以形成具有特定厚度的选择性氧化膜。 在该过程之后，p型和n型杂质从主表面双重扩散以限定通道的长度并形成基层和源层。 此外，n +型半导体衬底被指定为漏极层。 在双扩散之后，通过栅极氧化膜形成栅电极，形成源电极和漏电极。

公开(公告)号：US5470770A

公开(公告)日：1995-11-28

申请号：US413404

申请日：1995-03-30

申请人： Shigeki Takahashi ,  Mitsuhiro Kataoka ,  Tsuyoshi Yamamoto

发明人： Shigeki Takahashi ,  Mitsuhiro Kataoka ,  Tsuyoshi Yamamoto

IPC分类号： H01L21/316 ,  H01L21/336 ,  H01L29/78 ,  H01L21/8234

CPC分类号： H01L21/02255 ,  H01L21/02238 ,  H01L21/31662 ,  H01L29/7813 ,  Y10S148/126

摘要： A manufacturing method for a semiconductor device, which can attain a low ion voltage in a manufacturing method for a semiconductor device involving a process for forming a groove by etching prior to selective oxidation, selectively oxidizing a region including the groove and thereby making a channel part of the groove, is disclosed. A groove part is thermally oxidized by using a silicon nitride film as a mask. A LOCOS oxide film is formed by this thermal oxidation, and concurrently a U-groove is formed on the surface of an n.sup.- -type epitaxial layer eroded by the LOCOS oxide film, and the shape of the U-groove is fixed. A curve part formed during a chemical dry etching process remains as a curve part on the side surface of the U-groove. Then, an n.sup.+ -type source layer is formed by means of thermal diffusion to a junction thickness of 0.5 to 1 .mu.m, and a channel is set up as well. The junction depth obtained by this thermal diffusion is set up more deeply than the curve part which is formed during the above etching and remains on the side surface of the U-groove after the above selective thermal oxidation.

摘要翻译： 一种用于半导体器件的制造方法的半导体器件的制造方法，其包括在选择性氧化之前通过蚀刻形成沟槽的工艺的半导体器件的制造方法，选择性地氧化包括沟槽的区域，从而形成沟道部分 的凹槽。 通过使用氮化硅膜作为掩模将槽部热氧化。 通过该热氧化形成LOCOS氧化物膜，并且在由LOCOS氧化物膜侵蚀的n型外延层的表面上形成U形槽，并且U形槽的形状被固定。 在化学干蚀刻过程中形成的曲线部分在U形槽的侧表面上保持为曲线部分。 然后，通过热扩散形成0.5±1μm的结合厚度的n +型源极层，并且还设置沟道。 通过该热扩散获得的结深度比在上述蚀刻期间形成的曲线部分更深地设置，并且在上述选择性热氧化之后保留在U形槽的侧表面上。

公开(公告)号：US5453390A

公开(公告)日：1995-09-26

申请号：US38958

申请日：1993-03-29

申请人： Toshiaki Nishizawa ,  Akira Kuroyanagi ,  Tsuyoshi Yamamoto ,  Norihito Tokura

发明人： Toshiaki Nishizawa ,  Akira Kuroyanagi ,  Tsuyoshi Yamamoto ,  Norihito Tokura

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L27/02 ,  H01L27/04 ,  H01L21/266

CPC分类号： H01L29/66712 ,  H01L27/0248 ,  H01L29/7811 ,  H01L29/7815 ,  Y10S148/126

摘要： A power semiconductor device having current detecting function comprising a detection pert that includes the elements of a better reach-through withstand voltage capability than those of a principal current part. The power semiconductor device comprises such elements as DMOS, IGBT or BPT cells. One area of the device acts as the detection part and another as the principal current part. The detection part and the principal current part share as their common electrode a high density substrate having a low density layer of a first conductivity type. The surface of the low density layer carries a principal and a subordinate well region of a second conductivity type each. The surface of the principal well region bears a surface electrode region of the first conductivity type acting as the other electrode of the principal current part; the surface of the subordinate well region carries a surface electrode region of the first conductivity type acting as the other electrode of the detection part. The subordinate well region is made shallower than the principal well region illustratively by use of a mask having narrower apertures through which to form the former region. This causes a reach-through to occur in the principal current part with its well region having a shorter distance to the high density substrate, and not in the detection part with its well region having a longer distance to the substrate.

摘要翻译： 一种具有电流检测功能的功率半导体器件，包括具有比主要电流部分更好的达到耐受电压能力的元件的检测灵敏度。 功率半导体器件包括诸如DMOS，IGBT或BPT单元的元件。 设备的一个区域作为检测部分，另一个作为主要的当前部分。 检测部分和主要电流部分共同作为其公共电极具有第一导电类型的低密度层的高密度基板。 低密度层的表面分别载有第二导电类型的主要和次要的阱区。 主阱区域的表面具有作为主电流部分的另一个电极的第一导电类型的表面电极区域; 下位阱区域的表面带有用作检测部分的另一电极的第一导电类型的表面电极区域。 通过使用具有较窄孔径的掩模来形成下一个井区域使其比主井区域浅，以形成前区域。 这导致在主电流部分中出现通孔，其阱区具有与高密度衬底相距较短的距离，而不在其阱区具有与衬底相距较远的检测部分中。

公开(公告)号：US5654560A

公开(公告)日：1997-08-05

申请号：US475096

申请日：1995-06-07

申请人： Toshiaki Nishizawa ,  Akira Kuroyanagi ,  Tsuyoshi Yamamoto ,  Norihito Tokura

发明人： Toshiaki Nishizawa ,  Akira Kuroyanagi ,  Tsuyoshi Yamamoto ,  Norihito Tokura

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L27/02 ,  H01L27/04 ,  H01L29/74

CPC分类号： H01L29/66712 ,  H01L27/0248 ,  H01L29/7811 ,  H01L29/7815 ,  Y10S148/126

摘要： A power semiconductor device having a current detecting function comprising a detection part that includes the elements of a better reach-through withstand voltage capability than those of a principal current part. The power semiconductor device comprises such elements as DMOS, IGBT or BPT cells. One area of the device acts as the detection part and another as the principal current part. The detection part and the principal current part share as their common electrode a high density substrate having a low density layer of a first conductivity type. The surface of the low density layer carries a principal and a subordinate well region of a second conductivity type each. The surface of the principal well region bears a surface electrode region of the first conductivity type acting as the other electrode of the principal current part; the surface of the subordinate well region carries a surface electrode region of the first conductivity type acting as the other electrode of the detection part. The subordinate well region is made shallower than the principal well region illustratively by use of a mask having narrower apertures through which to form the former region. This causes a reach-through to occur in the principal current part with its well region having a shorter distance to the high density substrate, and not in the detection part with its well region having a longer distance to the substrate.

摘要翻译： 一种具有电流检测功能的功率半导体器件，包括检测部件，该检测部件包括比主电流部件更好的达到耐受电压能力的元件。 功率半导体器件包括诸如DMOS，IGBT或BPT单元的元件。 设备的一个区域作为检测部分，另一个作为主要的当前部分。 检测部分和主要电流部分共同作为其公共电极具有第一导电类型的低密度层的高密度基板。 低密度层的表面分别载有第二导电类型的主要和次要的阱区。 主阱区域的表面具有作为主电流部分的另一个电极的第一导电类型的表面电极区域; 下位阱区域的表面带有用作检测部分的另一电极的第一导电类型的表面电极区域。 通过使用具有较窄孔径的掩模来形成下一个井区域使其比主井区域浅，以形成前区域。 这导致在主电流部分中出现通孔，其阱区具有与高密度衬底相距较短的距离，而不在其阱区具有与衬底相距较远的检测部分中。

公开(公告)号：US5365085A

公开(公告)日：1994-11-15

申请号：US735512

申请日：1991-07-29

申请人： Norihito Tokura ,  Tsuyoshi Yamamoto

发明人： Norihito Tokura ,  Tsuyoshi Yamamoto

IPC分类号： G05F1/56 ,  H01L27/02 ,  H01L27/04 ,  H01L29/06 ,  H01L29/78 ,  H01L29/74 ,  H01L31/111 ,  H01L29/00 ,  H01L27/082

CPC分类号： H01L29/7813 ,  H01L27/0248 ,  H01L29/7815

摘要： A power semiconductor device constituted of a MOSFET incorporating a current detecting function for detecting current making use of a voltage drop developed across a channel resistance in which variations in the channel resistance due to its temperature and the gate voltage are compensated for and thereby highly accurate current detection is achieved.

摘要翻译： 一种功率半导体器件，其由具有电流检测功能的MOSFET构成，该MOSFET用于检测利用在沟道电阻上产生的电压降的电流，其中由于其温度和栅极电压导致的沟道电阻的变化被补偿，并由此高精度的电流 实现检测。

公开(公告)号：US6100140A

公开(公告)日：2000-08-08

申请号：US675774

申请日：1996-07-03

申请人： Naoto Okabe ,  Tsuyoshi Yamamoto ,  Mitsuhiro Kataoka

发明人： Naoto Okabe ,  Tsuyoshi Yamamoto ,  Mitsuhiro Kataoka

IPC分类号： H01L21/324 ,  H01L21/336 ,  H01L29/739 ,  H01L29/78

CPC分类号： H01L29/7813

摘要： A manufacturing method of a vertical type MOSFET, which can suppress vaporization of impurity from a semiconductor substrate and prevent variation in carrier density of the channel, is disclosed. The vertical type MOSFET is formed by forming a local oxide film to form a concavity on the element surface, removing the local oxide film by wet-etching technique, forming the gate oxide film at the sidewall of the concavity by thermal oxidation, and forming a gate electrode. Further, a polycrystalline silicon is formed on a back surface of the semiconductor substrate before removing the local oxide film. Accordingly, since the polycrystalline silicon is not removed when removing the local oxide film, vaporization of impurity from the semiconductor substrate is suppressed during the thermal oxidation for forming the gate oxide film, thereby preventing change in the carrier density of the channel.

摘要翻译： 公开了一种垂直型MOSFET的制造方法，其可以抑制杂质从半导体衬底蒸发并防止沟道的载流子密度的变化。 垂直型MOSFET通过形成局部氧化膜以在元件表面上形成凹陷而形成，通过湿蚀刻技术去除局部氧化膜，通过热氧化在凹部的侧壁处形成栅极氧化膜，并形成 栅电极。 此外，在去除局部氧化物膜之前，在半导体衬底的背面上形成多晶硅。 因此，由于在去除局部氧化膜时不去除多晶硅，因此在形成栅极氧化膜的热氧化期间抑制了半导体衬底的杂质蒸发，从而防止了沟道的载流子密度的变化。

公开(公告)号：US5925911A

公开(公告)日：1999-07-20

申请号：US638374

申请日：1996-04-26

申请人： Naoto Okabe ,  Tsuyoshi Yamamoto ,  Mitsuhiro Kataoka

发明人： Naoto Okabe ,  Tsuyoshi Yamamoto ,  Mitsuhiro Kataoka

IPC分类号： H01L21/322 ,  H01L21/336 ,  H01L29/739 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L29/7397 ,  H01L21/3221 ,  H01L29/7809 ,  H01L29/7813

摘要： A semiconductor device having a concavity formed by LOCOS technique, in which defects induced due to the LOCOS oxidation step or a following heat-treatment step are suppressed, is disclosed. An n.sup.+ type region, the impurity concentration of which is caused to be 1.times.10.sup.19 cm.sup.-3 or more, is formed in an n.sup.- type semiconductor layer. By means of this, defects occur within the n.sup.+ type region or in a proximity of the boundary of the n.sup.+ type region and the n.sup.- type semiconductor layer. The defects trap contaminant impurities taken into the wafer during the manufacturing steps, and cause contaminant impurities existing in the proximity of a concavity of the semiconductor surface to be reduced. As a result thereof, defect occurrence in the proximity of the concavity can be suppressed, and occurrence of leakage and degradation in breakdown voltage between drain and source accompanying defect occurrence in a channel region can be suppressed.

摘要翻译： 公开了一种具有通过LOCOS技术形成的凹陷的半导体器件，其中抑制了由于LOCOS氧化步骤或随后的热处理步骤引起的缺陷。 在n-型半导体层中形成其杂质浓度为1×1019 cm -3以上的n +型区域。 借此，在n +型区域或n +型区域和n型半导体层的边界附近发生缺陷。 这些缺陷会在制造步骤期间捕获杂质吸收到晶片中，并且导致存在于半导体表面的凹部附近的污染物杂质减少。 结果，可以抑制在凹部附近的缺陷发生，并且可以抑制在沟道区域中伴随缺陷发生的泄漏和源极之间的击穿电压的发生和劣化。