公开(公告)号：US5698880A

公开(公告)日：1997-12-16

申请号：US539380

申请日：1995-10-05

申请人： Shigeki Takahashi ,  Mitsuhiro Kataoka ,  Tsuyoshi Yamamoto ,  Yuuichi Takeuchi ,  Norihito Tokura

发明人： Shigeki Takahashi ,  Mitsuhiro Kataoka ,  Tsuyoshi Yamamoto ,  Yuuichi Takeuchi ,  Norihito Tokura

IPC分类号： H01L21/336 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： Y02E10/50

摘要： A manufacturing method for a semiconductor device, which can attain a low ion voltage in a manufacturing method for a semiconductor device involving a process for forming a groove by etching prior to selective oxidation, selectively oxidizing a region including the groove and thereby making a channel part of the groove, is disclosed. A groove part is thermally oxidized by using a silicon nitride film as a mask. A LOCOS oxide film is formed by this thermal oxidation, and concurrently a U-groove is formed on the surface of an n.sup.- -type epitaxial layer eroded by the LOCOS oxide film, and the shape of the U-groove is fixed. A curve part formed during a chemical dry etching process remains as a curve part on the side surface of the U-groove. Then, an n.sup.+ -type source layer is formed by means of thermal diffusion to a junction thickness of 0.5 to 1 .mu.m, and a channel is set up as well. The junction depth obtained by this thermal diffusion is set up more deeply than the curve part which is formed during the above etching and remains on the side surface of the U-groove after the above selective thermal oxidation.

摘要翻译： 一种用于半导体器件的制造方法的半导体器件的制造方法，其包括在选择性氧化之前通过蚀刻形成沟槽的工艺的半导体器件的制造方法，选择性地氧化包括沟槽的区域，从而形成沟道部分 的凹槽。 通过使用氮化硅膜作为掩模将槽部热氧化。 通过该热氧化形成LOCOS氧化物膜，并且在由LOCOS氧化物膜侵蚀的n型外延层的表面上形成U形槽，并且U形槽的形状被固定。 在化学干蚀刻过程中形成的曲线部分在U形槽的侧表面上保持为曲线部分。 然后，通过热扩散形成0.5±1μm的结合厚度的n +型源极层，并且还设置沟道。 通过该热扩散获得的结深度比在上述蚀刻期间形成的曲线部分更深地设置，并且在上述选择性热氧化之后保留在U形槽的侧表面上。

公开(公告)号：US5780324A

公开(公告)日：1998-07-14

申请号：US605637

申请日：1996-02-22

申请人： Norihito Tokura ,  Shigeki Takahashi ,  Tsuyoshi Yamamoto ,  Mitsuhiro Kataoka ,  Kunihiko Hara

发明人： Norihito Tokura ,  Shigeki Takahashi ,  Tsuyoshi Yamamoto ,  Mitsuhiro Kataoka ,  Kunihiko Hara

IPC分类号： H01L21/336 ,  H01L29/04 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L21/332

CPC分类号： H01L29/7813 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/4236

摘要： A manufacturing method of a vertical DMOSFET having a concave channel structure, which does not permit the introduction of defects or contaminant into the channel part and which can make the shape of the groove uniform, is disclosed. On a surface of a (100)-oriented n.sup.- -on-n.sup.+ epitaxial wafer is formed an initial groove by chemical dry etching. The grooved surface is then oxidized by LOCOS technique to form a LOCOS oxide film, whereby the concave structure is formed on the epitaxial wafer. The concave width is set to be at least twice the concave depth, and the sidewall angle is set to be approximately 50.degree. to make the sidewall plane (111) of high channel mobility plane. Following this process, p-type and n-type impurities are diffused from the main surface using the LOCOS oxide film as a double diffusion mask to form a body region and a source region.

摘要翻译： 公开了一种具有凹槽结构的垂直DMOSFET的制造方法，其不允许将缺陷或污染物引入通道部分并且可以使凹槽的形状均匀。 在（100）取向的n-on + n外延晶片的表面上，通过化学干蚀刻形成初始槽。 然后通过LOCOS技术将开槽的表面氧化以形成LOCOS氧化物膜，由此在外延晶片上形成凹形结构。 凹形宽度被设定为凹入深度的至少两倍，并且将侧壁角度设定为大约50°以使高通道迁移面的侧壁平面（111）。 在该过程之后，使用LOCOS氧化物膜作为双扩散掩模，从主表面扩散p型和n型杂质，以形成体区和源区。

公开(公告)号：US5470770A

公开(公告)日：1995-11-28

申请号：US413404

申请日：1995-03-30

申请人： Shigeki Takahashi ,  Mitsuhiro Kataoka ,  Tsuyoshi Yamamoto

发明人： Shigeki Takahashi ,  Mitsuhiro Kataoka ,  Tsuyoshi Yamamoto

IPC分类号： H01L21/316 ,  H01L21/336 ,  H01L29/78 ,  H01L21/8234

CPC分类号： H01L21/02255 ,  H01L21/02238 ,  H01L21/31662 ,  H01L29/7813 ,  Y10S148/126

摘要： A manufacturing method for a semiconductor device, which can attain a low ion voltage in a manufacturing method for a semiconductor device involving a process for forming a groove by etching prior to selective oxidation, selectively oxidizing a region including the groove and thereby making a channel part of the groove, is disclosed. A groove part is thermally oxidized by using a silicon nitride film as a mask. A LOCOS oxide film is formed by this thermal oxidation, and concurrently a U-groove is formed on the surface of an n.sup.- -type epitaxial layer eroded by the LOCOS oxide film, and the shape of the U-groove is fixed. A curve part formed during a chemical dry etching process remains as a curve part on the side surface of the U-groove. Then, an n.sup.+ -type source layer is formed by means of thermal diffusion to a junction thickness of 0.5 to 1 .mu.m, and a channel is set up as well. The junction depth obtained by this thermal diffusion is set up more deeply than the curve part which is formed during the above etching and remains on the side surface of the U-groove after the above selective thermal oxidation.

摘要翻译： 一种用于半导体器件的制造方法的半导体器件的制造方法，其包括在选择性氧化之前通过蚀刻形成沟槽的工艺的半导体器件的制造方法，选择性地氧化包括沟槽的区域，从而形成沟道部分 的凹槽。 通过使用氮化硅膜作为掩模将槽部热氧化。 通过该热氧化形成LOCOS氧化物膜，并且在由LOCOS氧化物膜侵蚀的n型外延层的表面上形成U形槽，并且U形槽的形状被固定。 在化学干蚀刻过程中形成的曲线部分在U形槽的侧表面上保持为曲线部分。 然后，通过热扩散形成0.5±1μm的结合厚度的n +型源极层，并且还设置沟道。 通过该热扩散获得的结深度比在上述蚀刻期间形成的曲线部分更深地设置，并且在上述选择性热氧化之后保留在U形槽的侧表面上。

公开(公告)号：US6015737A

公开(公告)日：2000-01-18

申请号：US515176

申请日：1995-08-15

申请人： Norihito Tokura ,  Shigeki Takahashi ,  Tsuyoshi Yamamoto ,  Mitsuhiro Kataoka

发明人： Norihito Tokura ,  Shigeki Takahashi ,  Tsuyoshi Yamamoto ,  Mitsuhiro Kataoka

IPC分类号： H01L21/336 ,  H01L29/04 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/045 ,  H01L29/0696 ,  H01L29/7813 ,  H01L29/4236

摘要： A vertical type power MOSFET remarkably reduces its ON-resistance per area. A substantial groove formation in which a gate structure is constituted is performed beforehand utilizing the LOCOS method before the formation of a p-type base layer and an n.sup.+ -type source layer. The p-type base layer and the n.sup.+ -type source layer are then formed by double diffusion in a manner of self-alignment with respect to a LOCOS oxide film, simultaneously with which channels are set at sidewall portions of the LOCOS oxide film. Thereafter the LOCOS oxide film is removed to provide a U-groove so as to constitute the gate structure. Namely, the channels are set by the double diffusion of the manner of self-alignment with respect to the LOCOS oxide film, so that the channels, which are set at the sidewall portions at both sides of the groove, provide a structure of exact bilateral symmetry, there is no positional deviation of the U-groove with respect to the base layer end, and the length of the bottom face of the U-groove can be made minimally short. Therefore, the unit cell size is greatly reduced, and the ON-resistance per area is greatly decreased.

摘要翻译： 垂直型功率MOSFET可显着降低每个区域的导通电阻。 在形成p型基极层和n +型源极层之前，利用LOCOS方法预先利用构成栅极结构的实质的槽形成。 然后通过相对于LOCOS氧化物膜的自对准的双扩散形成p型基极层和n +型源极层，同时将通道设置在LOCOS氧化物膜的侧壁部分。 此后，去除LOCOS氧化物膜以提供U形槽以构成栅极结构。 即，通过相对于LOCOS氧化膜的自对准方式的双扩散来设定通道，使得设置在凹槽两侧的侧壁部分处的通道提供精确双边的结构 U形槽相对于基底层端部没有位置偏离，U槽的底面的长度最短。 因此，单元电池尺寸大大降低，并且每个面积的导通电阻大大降低。

公开(公告)号：US5776812A

公开(公告)日：1998-07-07

申请号：US413410

申请日：1995-03-30

申请人： Shigeki Takahashi ,  Mitsuhiro Kataoka ,  Tsuyoshi Yamamoto ,  Yuuchi Takeuchi ,  Norihito Tokura

发明人： Shigeki Takahashi ,  Mitsuhiro Kataoka ,  Tsuyoshi Yamamoto ,  Yuuchi Takeuchi ,  Norihito Tokura

IPC分类号： H01L21/336 ,  H01L29/04 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/0696 ,  H01L29/045 ,  H01L29/7813 ,  H01L29/4236

摘要： A manufacturing method of a MOSFET having a channel part on the side surface of a groove, which does not permit the introduction of defects or contaminant into the channel part and which can make the shape of the groove uniform. An n.sup.- -type epitaxial layer having a low impurity concentration is formed on a main surface of an n.sup.+ -type semiconductor substrate. This surface is specified as a main surface, and chemical dry etching is applied to a specified region of this main surface. A region including a surface generated by the chemical dry etching is selectively oxidized to form a selective oxide film to a specified thickness. Following this process, p-type and n-type impurities are doubly diffused from the main surface to define the length of the channel and form a base layer and a source layer. Furthermore, the n.sup.+ -type semiconductor substrate is specified as a drain layer. After the double diffusion, a gate electrode is formed through a gate oxide film and a source electrode and a drain electrode are formed.

摘要翻译： 一种MOSFET的制造方法，其具有在槽的侧面上的通道部分，其不允许将缺陷或污染物引入通道部分中并且可以使槽的形状均匀。 在n +型半导体衬底的主表面上形成具有低杂质浓度的n型外延层。 该表面被指定为主表面，并且化学干蚀刻被施加到该主表面的指定区域。 包括通过化学干蚀刻生成的表面的区域被选择性地氧化以形成具有特定厚度的选择性氧化膜。 在该过程之后，p型和n型杂质从主表面双重扩散以限定通道的长度并形成基层和源层。 此外，n +型半导体衬底被指定为漏极层。 在双扩散之后，通过栅极氧化膜形成栅电极，形成源电极和漏电极。

公开(公告)号：US6100140A

公开(公告)日：2000-08-08

申请号：US675774

申请日：1996-07-03

申请人： Naoto Okabe ,  Tsuyoshi Yamamoto ,  Mitsuhiro Kataoka

发明人： Naoto Okabe ,  Tsuyoshi Yamamoto ,  Mitsuhiro Kataoka

IPC分类号： H01L21/324 ,  H01L21/336 ,  H01L29/739 ,  H01L29/78

CPC分类号： H01L29/7813

摘要： A manufacturing method of a vertical type MOSFET, which can suppress vaporization of impurity from a semiconductor substrate and prevent variation in carrier density of the channel, is disclosed. The vertical type MOSFET is formed by forming a local oxide film to form a concavity on the element surface, removing the local oxide film by wet-etching technique, forming the gate oxide film at the sidewall of the concavity by thermal oxidation, and forming a gate electrode. Further, a polycrystalline silicon is formed on a back surface of the semiconductor substrate before removing the local oxide film. Accordingly, since the polycrystalline silicon is not removed when removing the local oxide film, vaporization of impurity from the semiconductor substrate is suppressed during the thermal oxidation for forming the gate oxide film, thereby preventing change in the carrier density of the channel.

摘要翻译： 公开了一种垂直型MOSFET的制造方法，其可以抑制杂质从半导体衬底蒸发并防止沟道的载流子密度的变化。 垂直型MOSFET通过形成局部氧化膜以在元件表面上形成凹陷而形成，通过湿蚀刻技术去除局部氧化膜，通过热氧化在凹部的侧壁处形成栅极氧化膜，并形成 栅电极。 此外，在去除局部氧化物膜之前，在半导体衬底的背面上形成多晶硅。 因此，由于在去除局部氧化膜时不去除多晶硅，因此在形成栅极氧化膜的热氧化期间抑制了半导体衬底的杂质蒸发，从而防止了沟道的载流子密度的变化。

公开(公告)号：US5925911A

公开(公告)日：1999-07-20

申请号：US638374

申请日：1996-04-26

申请人： Naoto Okabe ,  Tsuyoshi Yamamoto ,  Mitsuhiro Kataoka

发明人： Naoto Okabe ,  Tsuyoshi Yamamoto ,  Mitsuhiro Kataoka

IPC分类号： H01L21/322 ,  H01L21/336 ,  H01L29/739 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L29/7397 ,  H01L21/3221 ,  H01L29/7809 ,  H01L29/7813

摘要： A semiconductor device having a concavity formed by LOCOS technique, in which defects induced due to the LOCOS oxidation step or a following heat-treatment step are suppressed, is disclosed. An n.sup.+ type region, the impurity concentration of which is caused to be 1.times.10.sup.19 cm.sup.-3 or more, is formed in an n.sup.- type semiconductor layer. By means of this, defects occur within the n.sup.+ type region or in a proximity of the boundary of the n.sup.+ type region and the n.sup.- type semiconductor layer. The defects trap contaminant impurities taken into the wafer during the manufacturing steps, and cause contaminant impurities existing in the proximity of a concavity of the semiconductor surface to be reduced. As a result thereof, defect occurrence in the proximity of the concavity can be suppressed, and occurrence of leakage and degradation in breakdown voltage between drain and source accompanying defect occurrence in a channel region can be suppressed.

摘要翻译： 公开了一种具有通过LOCOS技术形成的凹陷的半导体器件，其中抑制了由于LOCOS氧化步骤或随后的热处理步骤引起的缺陷。 在n-型半导体层中形成其杂质浓度为1×1019 cm -3以上的n +型区域。 借此，在n +型区域或n +型区域和n型半导体层的边界附近发生缺陷。 这些缺陷会在制造步骤期间捕获杂质吸收到晶片中，并且导致存在于半导体表面的凹部附近的污染物杂质减少。 结果，可以抑制在凹部附近的缺陷发生，并且可以抑制在沟道区域中伴随缺陷发生的泄漏和源极之间的击穿电压的发生和劣化。

公开(公告)号：US06573534B1

公开(公告)日：2003-06-03

申请号：US09265582

申请日：1999-03-10

申请人： Rajesh Kumar ,  Tsuyoshi Yamamoto ,  Shoichi Onda ,  Mitsuhiro Kataoka ,  Kunihiko Hara ,  Eiichi Okuno ,  Jun Kojima

发明人： Rajesh Kumar ,  Tsuyoshi Yamamoto ,  Shoichi Onda ,  Mitsuhiro Kataoka ,  Kunihiko Hara ,  Eiichi Okuno ,  Jun Kojima

IPC分类号： H01L310312

CPC分类号： H01L29/7828 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/7838 ,  Y10S438/931

摘要： A semiconductor device, comprising: a semiconductor substrate comprising silicon carbide of a first conductivity type; a silicon carbide epitaxial layer of the first conductivity type; a first semiconductor region formed on the semiconductor substrate and comprising silicon carbide of a second conductivity type; a second semiconductor region formed on the first semiconductor region, comprising silicon carbide of the first conductivity type and separated from the semiconductor substrate of the first conductivity type by the first semiconductor region; a third semiconductor region formed on the semiconductor region, connected to the semiconductor substrate and the second semiconductor region, comprising silicon carbide of the first conductivity type, and of higher resistance than the semiconductor substrate; and a gate electrode formed on the third semiconductor region via an insulating layer; wherein the third semiconductor layer is depleted when no voltage is being applied to the gate electrode so that said semiconductor device has a normally OFF characteristic.

摘要翻译： 一种半导体器件，包括：包含第一导电类型的碳化硅的半导体衬底; 第一导电类型的碳化硅外延层; 形成在所述半导体衬底上并且包括第二导电类型的碳化硅的第一半导体区域; 形成在所述第一半导体区域上的第二半导体区域，包括所述第一导电类型的碳化硅并且通过所述第一半导体区域与所述第一导电类型的半导体衬底分离; 形成在所述半导体区域上的第三半导体区域，与所述半导体衬底和所述第二半导体区域连接，所述第二半导体区域包括所述第一导电型的碳化硅，并且具有比所述半导体衬底更高的电阻; 以及经由绝缘层形成在所述第三半导体区域上的栅电极; 其中当没有电压施加到所述栅电极时，所述第三半导体层被耗尽，使得所述半导体器件具有正常OFF特性。

公开(公告)号：US6054752A

公开(公告)日：2000-04-25

申请号：US107507

申请日：1998-06-30

申请人： Kazukuni Hara ,  Yuichi Takeuchi ,  Tsuyoshi Yamamoto ,  Rajesh Kumar ,  Mitsuhiro Kataoka

发明人： Kazukuni Hara ,  Yuichi Takeuchi ,  Tsuyoshi Yamamoto ,  Rajesh Kumar ,  Mitsuhiro Kataoka

IPC分类号： H01L21/04 ,  H01L29/06 ,  H01L29/24 ,  H01L29/78 ,  H01L29/34 ,  H01L29/40

CPC分类号： H01L29/7813 ,  H01L29/0611 ,  H01L29/0638 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/1608

摘要： A semiconductor device comprises a semiconductor substrate including a first conductivity type first semiconductor layer and a second conductivity type second semiconductor layer formed on the first semiconductor layer. A unit cell for controlling current flowing between a source electrode and a drain electrode is formed in the semiconductor substrate. A trench is formed in a peripheral region of the unit cell to form mesa structure. A field relaxing layer is formed between an insulating film on a side face of the second trench and both the first semiconductor layer and the second semiconductor layer in order to relax concentration of an electric field in the insulating film.

摘要翻译： 半导体器件包括：半导体衬底，包括形成在第一半导体层上的第一导电型第一半导体层和第二导电型第二半导体层。 在半导体衬底中形成用于控制在源电极和漏电极之间流动的电流的单元。 在单电池的周边区域形成沟槽，形成台面结构。 在第二沟槽的侧面上的绝缘膜与第一半导体层和第二半导体层之间形成场弛豫层，以使绝缘膜中的电场的集中化。

公开(公告)号：US20130005318A1

公开(公告)日：2013-01-03

申请号：US13519702

申请日：2010-12-27

申请人： Masayuki Motegi ,  Yoshitsugu Shimazu ,  Hidehiko Oyane ,  Tsuyoshi Yamamoto

发明人： Masayuki Motegi ,  Yoshitsugu Shimazu ,  Hidehiko Oyane ,  Tsuyoshi Yamamoto

IPC分类号： H04W4/00

CPC分类号： H04W24/08 ,  H04W88/10 ,  H04W92/12

摘要： In a BRE300, an RF interface for transmitting and receiving an RF signal is used for communication with a MDE 200 and a digital signal interface for transmitting and receiving a digital signal in accordance with CPRI is used for communication with BDE 300. The BRE 300 includes a monitoring signal interface configured to notify the MDE 200 of a monitoring signal indicating a state of the radio unit 50. The signal transmitted and received through the monitoring signal interface is a ground signal and is of type different from types of signals transmitted and received by the RF interface and the digital signal interface.

摘要翻译： 在BRE300中，用于发送和接收RF信号的RF接口用于与MDE 200进行通信，并且用于根据CPRI发送和接收数字信号的数字信号接口用于与BDE 300进行通信。BRE 300包括 监视信号接口，被配置为向MDE 200通知指示无线电单元50的状态的监视信号。通过监视信号接口发送和接收的信号是接地信号，并且类型与由信号发送和接收的信号的类型不同 RF接口和数字信号接口。