公开(公告)号：US5780324A

公开(公告)日：1998-07-14

申请号：US605637

申请日：1996-02-22

申请人： Norihito Tokura ,  Shigeki Takahashi ,  Tsuyoshi Yamamoto ,  Mitsuhiro Kataoka ,  Kunihiko Hara

发明人： Norihito Tokura ,  Shigeki Takahashi ,  Tsuyoshi Yamamoto ,  Mitsuhiro Kataoka ,  Kunihiko Hara

IPC分类号： H01L21/336 ,  H01L29/04 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L21/332

CPC分类号： H01L29/7813 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/4236

摘要： A manufacturing method of a vertical DMOSFET having a concave channel structure, which does not permit the introduction of defects or contaminant into the channel part and which can make the shape of the groove uniform, is disclosed. On a surface of a (100)-oriented n.sup.- -on-n.sup.+ epitaxial wafer is formed an initial groove by chemical dry etching. The grooved surface is then oxidized by LOCOS technique to form a LOCOS oxide film, whereby the concave structure is formed on the epitaxial wafer. The concave width is set to be at least twice the concave depth, and the sidewall angle is set to be approximately 50.degree. to make the sidewall plane (111) of high channel mobility plane. Following this process, p-type and n-type impurities are diffused from the main surface using the LOCOS oxide film as a double diffusion mask to form a body region and a source region.

摘要翻译： 公开了一种具有凹槽结构的垂直DMOSFET的制造方法，其不允许将缺陷或污染物引入通道部分并且可以使凹槽的形状均匀。 在（100）取向的n-on + n外延晶片的表面上，通过化学干蚀刻形成初始槽。 然后通过LOCOS技术将开槽的表面氧化以形成LOCOS氧化物膜，由此在外延晶片上形成凹形结构。 凹形宽度被设定为凹入深度的至少两倍，并且将侧壁角度设定为大约50°以使高通道迁移面的侧壁平面（111）。 在该过程之后，使用LOCOS氧化物膜作为双扩散掩模，从主表面扩散p型和n型杂质，以形成体区和源区。

公开(公告)号：US06573534B1

公开(公告)日：2003-06-03

申请号：US09265582

申请日：1999-03-10

申请人： Rajesh Kumar ,  Tsuyoshi Yamamoto ,  Shoichi Onda ,  Mitsuhiro Kataoka ,  Kunihiko Hara ,  Eiichi Okuno ,  Jun Kojima

发明人： Rajesh Kumar ,  Tsuyoshi Yamamoto ,  Shoichi Onda ,  Mitsuhiro Kataoka ,  Kunihiko Hara ,  Eiichi Okuno ,  Jun Kojima

IPC分类号： H01L310312

CPC分类号： H01L29/7828 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/7838 ,  Y10S438/931

摘要： A semiconductor device, comprising: a semiconductor substrate comprising silicon carbide of a first conductivity type; a silicon carbide epitaxial layer of the first conductivity type; a first semiconductor region formed on the semiconductor substrate and comprising silicon carbide of a second conductivity type; a second semiconductor region formed on the first semiconductor region, comprising silicon carbide of the first conductivity type and separated from the semiconductor substrate of the first conductivity type by the first semiconductor region; a third semiconductor region formed on the semiconductor region, connected to the semiconductor substrate and the second semiconductor region, comprising silicon carbide of the first conductivity type, and of higher resistance than the semiconductor substrate; and a gate electrode formed on the third semiconductor region via an insulating layer; wherein the third semiconductor layer is depleted when no voltage is being applied to the gate electrode so that said semiconductor device has a normally OFF characteristic.

摘要翻译： 一种半导体器件，包括：包含第一导电类型的碳化硅的半导体衬底; 第一导电类型的碳化硅外延层; 形成在所述半导体衬底上并且包括第二导电类型的碳化硅的第一半导体区域; 形成在所述第一半导体区域上的第二半导体区域，包括所述第一导电类型的碳化硅并且通过所述第一半导体区域与所述第一导电类型的半导体衬底分离; 形成在所述半导体区域上的第三半导体区域，与所述半导体衬底和所述第二半导体区域连接，所述第二半导体区域包括所述第一导电型的碳化硅，并且具有比所述半导体衬底更高的电阻; 以及经由绝缘层形成在所述第三半导体区域上的栅电极; 其中当没有电压施加到所述栅电极时，所述第三半导体层被耗尽，使得所述半导体器件具有正常OFF特性。

公开(公告)号：US5504360A

公开(公告)日：1996-04-02

申请号：US293421

申请日：1994-08-22

申请人： Norihito Tokura ,  Kunihiko Hara

发明人： Norihito Tokura ,  Kunihiko Hara

IPC分类号： H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L29/7813 ,  H01L29/7802 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/41766

摘要： A vertical type semiconductor device is provided with an improved construction which greatly decreases the on-resistance without impairing the breakdown voltage thereof. In the fundamental DMOS cells that control a current to constitute the vertical semiconductor device, through-hole cells are arranged along the sides of a cell having a channel. The through-hole cell includes a through-hole extending from the surface of an n.sup.- -type drift region toward an n.sup.+ -type drain region, and also includes an n.sup.+ -type through-hole region that is formed by diffusing impurities from the inner wall of the through-hole which is continuous with the n.sup.+ -type drain region. A breakdown voltage of the element is maintained by the n.sup.- -type drift region between a p-type well region and the n.sup.+ -type through-hole region or the n.sup.+ -type drain region. Given the unique arrangement of the through-hole cells, the JFET resistance component becomes negligibly small between the DMOS cells neighboring along the sides of the cells despite the fact that the cells are finely formed, and a small on-resistance is exhibited.

摘要翻译： 垂直型半导体器件具有改进的结构，其大大降低导通电阻而不损害其击穿电压。 在控制电流以构成垂直半导体器件的基本DMOS单元中，沿着具有沟道的单元的侧面布置有通孔单元。 通孔单元包括从n型漂移区域的表面向n +型漏极区域延伸的通孔，还包括通过从内部扩散杂质形成的n +型通孔区域 与n +型漏极区连续的通孔的壁。 元件的击穿电压由p型阱区域和n +型通孔区域或n +型漏极区域之间的n型漂移区域维持。 鉴于通孔单元的独特布置，尽管细胞形成细小，但是出现小的导通电阻，但是JFET电阻分量在沿着单元侧面相邻的DMOS单元之间变得可以忽略不计。

公开(公告)号：US4962411A

公开(公告)日：1990-10-09

申请号：US307177

申请日：1989-02-03

申请人： Norihito Tokura ,  Hironari Kuno ,  Hiroyasu Ito ,  Hirohiko Saito ,  Kunihiko Hara

发明人： Norihito Tokura ,  Hironari Kuno ,  Hiroyasu Ito ,  Hirohiko Saito ,  Kunihiko Hara

IPC分类号： H01L27/02 ,  H01L29/78

CPC分类号： H01L29/7815 ,  H01L27/0248 ,  H01L29/423

摘要： A semiconductor device with a current detecting function in which in place of an external resistor for detecting an operation current such as drain current or collector current of a device such as an FET or bipolar transistor, a probe electrode is formed in proximity to the device depletion layer to connect therethrough with the device channel to generate a probe voltage corresponding to the operation current.

摘要翻译： 具有电流检测功能的半导体器件，其中代替用于检测诸如FET或双极晶体管的器件的漏极电流或集电极电流等工作电流的外部电阻器，形成探针电极附近的器件耗尽 层与器件通道连接以产生对应于工作电流的探针电压。

公开(公告)号：US5696396A

公开(公告)日：1997-12-09

申请号：US734132

申请日：1996-10-21

申请人： Norihito Tokura ,  Kunihiko Hara ,  Takeshi Miyajima

发明人： Norihito Tokura ,  Kunihiko Hara ,  Takeshi Miyajima

IPC分类号： H01L29/10 ,  H01L29/12 ,  H01L29/24 ,  H01L29/45 ,  H01L29/78 ,  H01L29/76 ,  H01L31/0312 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L29/7813 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/7802

摘要： A vertical MOSFET, which can control AC current flowing through a device only by the gate voltage, is obtained. On an n.sup.+ silicon layer is formed an n.sup.- silicon layer. Within the n.sup.- silicon layer is formed a p-body region. Within the p-body region is formed an n.sup.+ source region. On top of a substrate are formed a source electrode in contact only with the source region and a base electrode in contact only with the p-body region. The source electrode and the base electrode are connected to each other through a resistance at the outside. On a channel region is formed a gate electrode through a gate oxide film (insulating film). When the above semiconductor device is in the reverse bias conduction, the exciting current is controlled only by the gate voltage by setting the current flowing from a source terminal through the resistance to the base electrode, the p-body region and the n.sup.- silicon layer to be negligibly small as compared with the current flowing from the source terminal through the source electrode to the n.sup.+ source region, the channel region and the n.sup.- silicon layer.

摘要翻译： 可以获得只能通过栅极电压控制流过器件的交流电流的垂直MOSFET。 在n +硅层上形成n-硅层。 在n-硅层内形成p体区域。 在p体区内形成n +源区。 在基板顶部形成仅与源极区域接触的源极电极和仅与p体区域接触的基极电极。 源电极和基极通过外部的电阻彼此连接。 在沟道区域上通过栅极氧化膜（绝缘膜）形成栅电极。 当上述半导体器件处于反向偏压传导时，通过将从源极端子流过电流的电流设置到基极，p体区域和n-硅层，从而仅通过栅极电压来控制励磁电流 与源极端子通过源极电极流到n +源极区域，沟道区域和n-硅层的电流相比，可以忽略不计。

公开(公告)号：US6057558A

公开(公告)日：2000-05-02

申请号：US34344

申请日：1998-03-04

申请人： Tsuyoshi Yamamoto ,  Rajesh Kumar ,  Kunihiko Hara ,  Yuichi Takeuchi ,  Kazukuni Hara ,  Masami Naito

发明人： Tsuyoshi Yamamoto ,  Rajesh Kumar ,  Kunihiko Hara ,  Yuichi Takeuchi ,  Kazukuni Hara ,  Masami Naito

IPC分类号： H01L21/04 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/24 ,  H01L29/423 ,  H01L29/78 ,  H01L31/0312

CPC分类号： H01L29/0847 ,  H01L29/0626 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/66666 ,  H01L29/7828 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/4238

摘要： In a silicon carbide semiconductor device such as a trench gate type power MOSFET, the film thickness and the impurity concentration of a thin film silicon carbide semiconductor layer formed on a trench side face to constitute an accumulation-type channel-forming region and enable the device to operate with a low gate voltage, low on-resistance and low power loss are set so that on impression of a reverse bias voltage a pn junction between a P-type epitaxial layer and an n.sup.- -type epitaxial layer undergoes avalanche breakdown before the thin film silicon carbide semiconductor layer undergoes punch-through. By this means it is possible to obtain a target high source-drain withstand voltage.

摘要翻译： 在诸如沟槽栅型功率MOSFET的碳化硅半导体器件中，形成在沟槽侧面上的薄膜碳化硅半导体层的膜厚度和杂质浓度构成积聚型沟道形成区域，并使器件 以低栅极电压操作，设置低导通电阻和低功率损耗，使得在反向偏置电压的印象上，P型外延层和n型外延层之间的pn结在其之前经历雪崩击穿 薄膜碳化硅半导体层进行穿通。 通过这种方式，可以获得目标高的源极 - 漏极耐受电压。

公开(公告)号：US20110079707A1

公开(公告)日：2011-04-07

申请号：US12967604

申请日：2010-12-14

申请人： Kunihiko Hara ,  Hiroshi Kubo ,  Yasuyuki Endo ,  Masatoshi Kimura

发明人： Kunihiko Hara ,  Hiroshi Kubo ,  Yasuyuki Endo ,  Masatoshi Kimura

IPC分类号： H01L27/146

CPC分类号： H01L27/14603 ,  H01L27/14609 ,  H01L27/14621 ,  H01L27/14641 ,  H01L27/14645

摘要： In a pixel part, in a first active region, a photodiode and a transferring transistor are formed. In a second active region, a resetting transistor is formed. In a pixel part, in a first active region, a photodiode and a transferring transistor are formed. In a second active region, an amplifying transistor is formed. The first and second active regions are respectively the same in shape in image pixel parts. The resetting transistor and the amplifying transistor are shared by the pixel parts.

摘要翻译： 在像素部分中，在第一有源区中形成光电二极管和转移晶体管。 在第二有源区中，形成复位晶体管。 在像素部分中，在第一有源区中形成光电二极管和转移晶体管。 在第二有源区中形成放大晶体管。 图像像素部分中的第一和第二有源区域的形状分别相同。 复位晶体管和放大晶体管由像素部分共享。

公开(公告)号：US20100309356A1

公开(公告)日：2010-12-09

申请号：US12864674

申请日：2009-01-27

申请人： Isao Ihara ,  Kunihiko Hara ,  Makoto Inagaki ,  Hiroshi Kubo

发明人： Isao Ihara ,  Kunihiko Hara ,  Makoto Inagaki ,  Hiroshi Kubo

IPC分类号： H04N5/335

CPC分类号： H04N5/3658 ,  H04N5/374 ,  H04N5/3742

摘要： A solid state imaging device according to an aspect of the present invention includes: a pixel array (21) including pixel units arranged in rows and columns; a vertical shift register (26) which selects one of the rows of the pixel array (21); a column amplifier unit (22) including column amplifiers each of which is provided for a corresponding one of the columns and amplifies a column signal provided from the pixel unit included in the selected row; and a limiting circuit which limits an output voltage of the column amplifier to no more than a predetermined voltage that can be changed, wherein the limiting circuit changes the predetermined voltage according to switching between a normal mode and a high-sensitivity mode.

摘要翻译： 根据本发明的一个方面的固态成像装置包括：像素阵列（21），包括以行和列排列的像素单元; 选择像素阵列（21）的行之一的垂直移位寄存器（26）; 列列放大器单元（22），其包括列放大器，每个列放大器用于对应的一列，并放大从包括在所选行中的像素单元提供的列信号; 以及将列放大器的输出电压限制在不大于可以改变的预定电压的限制电路，其中限制电路根据正常模式和高灵敏度模式之间的切换来改变预定电压。

公开(公告)号：US07646891B2

公开(公告)日：2010-01-12

申请号：US10529202

申请日：2002-12-26

申请人： Hiroshi Kage ,  Kunihiko Hara

发明人： Hiroshi Kage ,  Kunihiko Hara

IPC分类号： G06K9/00 ,  G06K9/40 ,  G06K9/36 ,  H04N5/228 ,  H04N5/14 ,  H04N9/64

CPC分类号： H04N5/23277 ,  G06T5/003 ,  G06T5/50 ,  G06T7/20 ,  G06T2207/20201 ,  H04N5/23248 ,  H04N5/23254

摘要： There is provided an image processor and a method thereof for high-speed compensation for taken-image blurs produced by camera shakes or the like. In the first instance, a motion-detecting area is selected for each of two images taken by an image sensor. When projective data is calculated by means of computing in a predetermined direction pixels of the motion-detecting areas, the motion vector between the two images can be acquired based on the projective data. The image correlativity between the two images is then calculated in the direction that the motion vector designates; and the amount of pixel displacement between the two images is calculated based on the correlativity values acquired by the calculation. Moreover, the area that has been produced by displacing an image output area in a camera-shake compensation area designated in the second frame, by the pixel-displacement amount calculated by a displacement calculator is cut away from the camera-shake compensation area, and is outputted as an image for the image output area of the second frame.

摘要翻译： 提供了一种用于高速补偿由相机抖动等产生的拍摄图像模糊的图像处理器及其方法。 在第一种情况下，对由图像传感器拍摄的两幅图像中的每一幅图像选择运动检测区域。 当通过在预定方向上计算运动检测区域的像素来计算投影数据时，可以基于投影数据获取两个图像之间的运动矢量。 然后在运动矢量指定的方向上计算两个图像之间的图像相关性; 并且基于通过计算获得的相关性值来计算两个图像之间的像素位移量。 此外，通过将在第二帧中指定的相机抖动补偿区域中的图像输出区域移位由位移计算器计算出的像素位移量而产生的区域被切掉相机抖动补偿区域，并且 作为第二帧的图像输出区域的图像输出。

公开(公告)号：US20090040346A1

公开(公告)日：2009-02-12

申请号：US12089289

申请日：2006-08-28

申请人： Masayuki Masuyama ,  Kunihiko Hara ,  Masashi Murakami ,  Shinsuke Nezaki

发明人： Masayuki Masuyama ,  Kunihiko Hara ,  Masashi Murakami ,  Shinsuke Nezaki

IPC分类号： H04N5/335 ,  H04N5/225

CPC分类号： H04N5/3765 ,  H04N5/3456

摘要： A solid-state imaging device includes first-group pixels 41, second-group pixels 42 skipped during thinning drive, and a scanning section 13. The scanning section 13 drives each of the first-group pixels 41 to perform read operation of outputting the output signal and initializing the amount of the signal charge accumulated in the photoelectric conversion element to a first level, and also drives each of the second-group pixels 42 to perform discharge operation of initializing the amount of the signal charge accumulated in the photoelectric conversion element to a second level that is higher than the first level and lower than a saturation signal level of the photoelectric conversion element 12.

摘要翻译： 固态成像装置包括第一组像素41，稀疏驱动期间跳过的第二组像素42以及扫描部13.扫描部13驱动第一组像素41中的每一个以执行输出输出的读取操作 将累积在光电转换元件中的信号电荷的量信号并初始化为第一电平，并且驱动每个第二组像素42执行将在光电转换元件中累积的信号电荷的量初始化的放电操作，以 高于第一电平并低于光电转换元件12的饱和信号电平的第二电平。