公开(公告)号：US5698880A

公开(公告)日：1997-12-16

申请号：US539380

申请日：1995-10-05

申请人： Shigeki Takahashi ,  Mitsuhiro Kataoka ,  Tsuyoshi Yamamoto ,  Yuuichi Takeuchi ,  Norihito Tokura

发明人： Shigeki Takahashi ,  Mitsuhiro Kataoka ,  Tsuyoshi Yamamoto ,  Yuuichi Takeuchi ,  Norihito Tokura

IPC分类号： H01L21/336 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： Y02E10/50

摘要： A manufacturing method for a semiconductor device, which can attain a low ion voltage in a manufacturing method for a semiconductor device involving a process for forming a groove by etching prior to selective oxidation, selectively oxidizing a region including the groove and thereby making a channel part of the groove, is disclosed. A groove part is thermally oxidized by using a silicon nitride film as a mask. A LOCOS oxide film is formed by this thermal oxidation, and concurrently a U-groove is formed on the surface of an n.sup.- -type epitaxial layer eroded by the LOCOS oxide film, and the shape of the U-groove is fixed. A curve part formed during a chemical dry etching process remains as a curve part on the side surface of the U-groove. Then, an n.sup.+ -type source layer is formed by means of thermal diffusion to a junction thickness of 0.5 to 1 .mu.m, and a channel is set up as well. The junction depth obtained by this thermal diffusion is set up more deeply than the curve part which is formed during the above etching and remains on the side surface of the U-groove after the above selective thermal oxidation.

摘要翻译： 一种用于半导体器件的制造方法的半导体器件的制造方法，其包括在选择性氧化之前通过蚀刻形成沟槽的工艺的半导体器件的制造方法，选择性地氧化包括沟槽的区域，从而形成沟道部分 的凹槽。 通过使用氮化硅膜作为掩模将槽部热氧化。 通过该热氧化形成LOCOS氧化物膜，并且在由LOCOS氧化物膜侵蚀的n型外延层的表面上形成U形槽，并且U形槽的形状被固定。 在化学干蚀刻过程中形成的曲线部分在U形槽的侧表面上保持为曲线部分。 然后，通过热扩散形成0.5±1μm的结合厚度的n +型源极层，并且还设置沟道。 通过该热扩散获得的结深度比在上述蚀刻期间形成的曲线部分更深地设置，并且在上述选择性热氧化之后保留在U形槽的侧表面上。

公开(公告)号：US5780324A

公开(公告)日：1998-07-14

申请号：US605637

申请日：1996-02-22

申请人： Norihito Tokura ,  Shigeki Takahashi ,  Tsuyoshi Yamamoto ,  Mitsuhiro Kataoka ,  Kunihiko Hara

发明人： Norihito Tokura ,  Shigeki Takahashi ,  Tsuyoshi Yamamoto ,  Mitsuhiro Kataoka ,  Kunihiko Hara

IPC分类号： H01L21/336 ,  H01L29/04 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L21/332

CPC分类号： H01L29/7813 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/4236

摘要： A manufacturing method of a vertical DMOSFET having a concave channel structure, which does not permit the introduction of defects or contaminant into the channel part and which can make the shape of the groove uniform, is disclosed. On a surface of a (100)-oriented n.sup.- -on-n.sup.+ epitaxial wafer is formed an initial groove by chemical dry etching. The grooved surface is then oxidized by LOCOS technique to form a LOCOS oxide film, whereby the concave structure is formed on the epitaxial wafer. The concave width is set to be at least twice the concave depth, and the sidewall angle is set to be approximately 50.degree. to make the sidewall plane (111) of high channel mobility plane. Following this process, p-type and n-type impurities are diffused from the main surface using the LOCOS oxide film as a double diffusion mask to form a body region and a source region.

摘要翻译： 公开了一种具有凹槽结构的垂直DMOSFET的制造方法，其不允许将缺陷或污染物引入通道部分并且可以使凹槽的形状均匀。 在（100）取向的n-on + n外延晶片的表面上，通过化学干蚀刻形成初始槽。 然后通过LOCOS技术将开槽的表面氧化以形成LOCOS氧化物膜，由此在外延晶片上形成凹形结构。 凹形宽度被设定为凹入深度的至少两倍，并且将侧壁角度设定为大约50°以使高通道迁移面的侧壁平面（111）。 在该过程之后，使用LOCOS氧化物膜作为双扩散掩模，从主表面扩散p型和n型杂质，以形成体区和源区。

公开(公告)号：US6015737A

公开(公告)日：2000-01-18

申请号：US515176

申请日：1995-08-15

申请人： Norihito Tokura ,  Shigeki Takahashi ,  Tsuyoshi Yamamoto ,  Mitsuhiro Kataoka

发明人： Norihito Tokura ,  Shigeki Takahashi ,  Tsuyoshi Yamamoto ,  Mitsuhiro Kataoka

IPC分类号： H01L21/336 ,  H01L29/04 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/045 ,  H01L29/0696 ,  H01L29/7813 ,  H01L29/4236

摘要： A vertical type power MOSFET remarkably reduces its ON-resistance per area. A substantial groove formation in which a gate structure is constituted is performed beforehand utilizing the LOCOS method before the formation of a p-type base layer and an n.sup.+ -type source layer. The p-type base layer and the n.sup.+ -type source layer are then formed by double diffusion in a manner of self-alignment with respect to a LOCOS oxide film, simultaneously with which channels are set at sidewall portions of the LOCOS oxide film. Thereafter the LOCOS oxide film is removed to provide a U-groove so as to constitute the gate structure. Namely, the channels are set by the double diffusion of the manner of self-alignment with respect to the LOCOS oxide film, so that the channels, which are set at the sidewall portions at both sides of the groove, provide a structure of exact bilateral symmetry, there is no positional deviation of the U-groove with respect to the base layer end, and the length of the bottom face of the U-groove can be made minimally short. Therefore, the unit cell size is greatly reduced, and the ON-resistance per area is greatly decreased.

摘要翻译： 垂直型功率MOSFET可显着降低每个区域的导通电阻。 在形成p型基极层和n +型源极层之前，利用LOCOS方法预先利用构成栅极结构的实质的槽形成。 然后通过相对于LOCOS氧化物膜的自对准的双扩散形成p型基极层和n +型源极层，同时将通道设置在LOCOS氧化物膜的侧壁部分。 此后，去除LOCOS氧化物膜以提供U形槽以构成栅极结构。 即，通过相对于LOCOS氧化膜的自对准方式的双扩散来设定通道，使得设置在凹槽两侧的侧壁部分处的通道提供精确双边的结构 U形槽相对于基底层端部没有位置偏离，U槽的底面的长度最短。 因此，单元电池尺寸大大降低，并且每个面积的导通电阻大大降低。

公开(公告)号：US5776812A

公开(公告)日：1998-07-07

申请号：US413410

申请日：1995-03-30

申请人： Shigeki Takahashi ,  Mitsuhiro Kataoka ,  Tsuyoshi Yamamoto ,  Yuuchi Takeuchi ,  Norihito Tokura

发明人： Shigeki Takahashi ,  Mitsuhiro Kataoka ,  Tsuyoshi Yamamoto ,  Yuuchi Takeuchi ,  Norihito Tokura

IPC分类号： H01L21/336 ,  H01L29/04 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/0696 ,  H01L29/045 ,  H01L29/7813 ,  H01L29/4236

摘要： A manufacturing method of a MOSFET having a channel part on the side surface of a groove, which does not permit the introduction of defects or contaminant into the channel part and which can make the shape of the groove uniform. An n.sup.- -type epitaxial layer having a low impurity concentration is formed on a main surface of an n.sup.+ -type semiconductor substrate. This surface is specified as a main surface, and chemical dry etching is applied to a specified region of this main surface. A region including a surface generated by the chemical dry etching is selectively oxidized to form a selective oxide film to a specified thickness. Following this process, p-type and n-type impurities are doubly diffused from the main surface to define the length of the channel and form a base layer and a source layer. Furthermore, the n.sup.+ -type semiconductor substrate is specified as a drain layer. After the double diffusion, a gate electrode is formed through a gate oxide film and a source electrode and a drain electrode are formed.

摘要翻译： 一种MOSFET的制造方法，其具有在槽的侧面上的通道部分，其不允许将缺陷或污染物引入通道部分中并且可以使槽的形状均匀。 在n +型半导体衬底的主表面上形成具有低杂质浓度的n型外延层。 该表面被指定为主表面，并且化学干蚀刻被施加到该主表面的指定区域。 包括通过化学干蚀刻生成的表面的区域被选择性地氧化以形成具有特定厚度的选择性氧化膜。 在该过程之后，p型和n型杂质从主表面双重扩散以限定通道的长度并形成基层和源层。 此外，n +型半导体衬底被指定为漏极层。 在双扩散之后，通过栅极氧化膜形成栅电极，形成源电极和漏电极。

公开(公告)号：US5470770A

公开(公告)日：1995-11-28

申请号：US413404

申请日：1995-03-30

申请人： Shigeki Takahashi ,  Mitsuhiro Kataoka ,  Tsuyoshi Yamamoto

发明人： Shigeki Takahashi ,  Mitsuhiro Kataoka ,  Tsuyoshi Yamamoto

IPC分类号： H01L21/316 ,  H01L21/336 ,  H01L29/78 ,  H01L21/8234

CPC分类号： H01L21/02255 ,  H01L21/02238 ,  H01L21/31662 ,  H01L29/7813 ,  Y10S148/126

摘要： A manufacturing method for a semiconductor device, which can attain a low ion voltage in a manufacturing method for a semiconductor device involving a process for forming a groove by etching prior to selective oxidation, selectively oxidizing a region including the groove and thereby making a channel part of the groove, is disclosed. A groove part is thermally oxidized by using a silicon nitride film as a mask. A LOCOS oxide film is formed by this thermal oxidation, and concurrently a U-groove is formed on the surface of an n.sup.- -type epitaxial layer eroded by the LOCOS oxide film, and the shape of the U-groove is fixed. A curve part formed during a chemical dry etching process remains as a curve part on the side surface of the U-groove. Then, an n.sup.+ -type source layer is formed by means of thermal diffusion to a junction thickness of 0.5 to 1 .mu.m, and a channel is set up as well. The junction depth obtained by this thermal diffusion is set up more deeply than the curve part which is formed during the above etching and remains on the side surface of the U-groove after the above selective thermal oxidation.

摘要翻译： 一种用于半导体器件的制造方法的半导体器件的制造方法，其包括在选择性氧化之前通过蚀刻形成沟槽的工艺的半导体器件的制造方法，选择性地氧化包括沟槽的区域，从而形成沟道部分 的凹槽。 通过使用氮化硅膜作为掩模将槽部热氧化。 通过该热氧化形成LOCOS氧化物膜，并且在由LOCOS氧化物膜侵蚀的n型外延层的表面上形成U形槽，并且U形槽的形状被固定。 在化学干蚀刻过程中形成的曲线部分在U形槽的侧表面上保持为曲线部分。 然后，通过热扩散形成0.5±1μm的结合厚度的n +型源极层，并且还设置沟道。 通过该热扩散获得的结深度比在上述蚀刻期间形成的曲线部分更深地设置，并且在上述选择性热氧化之后保留在U形槽的侧表面上。

公开(公告)号：US5460985A

公开(公告)日：1995-10-24

申请号：US30338

申请日：1993-03-25

申请人： Norihito Tokura ,  Shigeki Takahashi

发明人： Norihito Tokura ,  Shigeki Takahashi

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/04 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L21/8232

CPC分类号： H01L29/0696 ,  H01L21/28167 ,  H01L29/045 ,  H01L29/7813 ,  H01L21/28211 ,  H01L29/4236 ,  Y10S148/116 ,  Y10S148/126

摘要： A vertical type power MOSFET remarkably reduces its ON-resistance per area. A substantial groove formation in which a gate structure is constituted is performed beforehand utilizing the LOCOS method before the formation of a p-type base layer and an n.sup.+ -type source layer. The p-type base layer and the n.sup.+ -type source layer are then formed by double diffusion in a manner of self-alignment with respect to a LOCOS oxide film, simultaneously with which channels are set at sidewall portions of the LOCOS oxide film. Thereafter the LOCOS oxide film is removed to provide a U-groove so as to constitute the gate structure. Namely, the channels are set by the double diffusion of the manner of self-alignment with respect to the LOCOS oxide film, so that the channels, which are set at the sidewall portions at both sides of the groove, provide a structure of exact bilateral symmetry, there is no positional deviation of the U-groove with respect to the base layer end, and the length of the bottom face of the U-groove can be made minimally short. Therefore, the unit cell size is greatly reduced, and the ON-resistance per area is greatly decreased.

摘要翻译： PCT No.PCT / JP92 / 00929 Sec。 371日期1993年3月25日 102（e）1993年3月25日PCT提交1992年7月22日PCT公布。 公开号WO93 / 03502 日期：1993年2月18日。垂直型功率MOSFET显着降低了其面积的导通电阻。 在形成p型基极层和n +型源极层之前，利用LOCOS方法预先利用构成栅极结构的实质的槽形成。 然后通过相对于LOCOS氧化物膜的自对准的双扩散形成p型基极层和n +型源极层，同时将通道设置在LOCOS氧化物膜的侧壁部分。 此后，去除LOCOS氧化物膜以提供U形槽以构成栅极结构。 即，通过相对于LOCOS氧化膜的自对准方式的双扩散来设定通道，使得设置在凹槽两侧的侧壁部分处的通道提供精确双边的结构 U形槽相对于基底层端部没有位置偏离，U槽的底面的长度最短。 因此，单元电池尺寸大大降低，并且每个面积的导通电阻大大降低。

公开(公告)号：US09240445B2

公开(公告)日：2016-01-19

申请号：US14113419

申请日：2012-05-10

申请人： Takashi Suzuki ,  Norihito Tokura ,  Satoshi Shiraki ,  Shigeki Takahashi ,  Youichi Ashida ,  Akira Yamada

发明人： Takashi Suzuki ,  Norihito Tokura ,  Satoshi Shiraki ,  Shigeki Takahashi ,  Youichi Ashida ,  Akira Yamada

IPC分类号： H01L23/62 ,  H01L29/06 ,  H01L29/40 ,  H01L29/861

CPC分类号： H01L29/063 ,  H01L29/0692 ,  H01L29/402 ,  H01L29/404 ,  H01L29/405 ,  H01L29/861

摘要： A lateral semiconductor device includes a semiconductor layer, an insulating layer, and a resistive field plate. The semiconductor layer includes a first semiconductor region and a second semiconductor region at a surface portion, and the second semiconductor region makes a circuit around the first semiconductor region. The insulating layer is formed on a surface of the semiconductor layer and is disposed between the first and second semiconductor regions. The resistive field plate is formed on a surface of the insulating layer. Between the first and second semiconductor regions, a first section and a second section are adjacent to each other along a circumferential direction around the first semiconductor region. The resistive field plate includes first and second resistive field plate sections respectively formed in the first and second sections, and the first and second resistive field plate sections are separated from each other.

摘要翻译： 横向半导体器件包括半导体层，绝缘层和电阻场板。 半导体层包括在表面部分处的第一半导体区域和第二半导体区域，并且第二半导体区域在第一半导体区域周围形成电路。 绝缘层形成在半导体层的表面上并且设置在第一和第二半导体区之间。 电阻场板形成在绝缘层的表面上。 在第一和第二半导体区域之间，第一部分和第二部分沿着围绕第一半导体区域的圆周方向彼此相邻。 电阻场板包括分别形成在第一和第二部分中的第一和第二电阻场板部分，并且第一和第二电阻场板部分彼此分离。

公开(公告)号：US06603173B1

公开(公告)日：2003-08-05

申请号：US09391236

申请日：1999-09-07

申请人： Yoshifumi Okabe ,  Yoshihiko Ozeki ,  Shigeki Takahashi ,  Norihito Tokura

发明人： Yoshifumi Okabe ,  Yoshihiko Ozeki ,  Shigeki Takahashi ,  Norihito Tokura

IPC分类号： H01L2976

CPC分类号： H01L29/7813 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/4236

摘要： A vertical power MOSFET, which can improve a surge withstand voltage and a surge withstand voltage against a surge voltage from an inductance load L. The vertical power MOSFET has a plurality of unit cells. The unit cell is formed from a MOSFET that uses a p-type base layer at a sidewall of a rectangular U-groove as a channel portion. Each of the p-type base layer of each unit cell is connected each others Accordingly, it can restrain an impurity concentration of a corner portion (a portion positioned at a corner) of the rectangular p-type base layer from being decreased. Therefore, it can reduce the difference in distance from the end portion of the p-type base layer to the end portion of the depletion layer. As a result, it can improve the surge withstand voltage when a surge voltage is input from an inductance load L.

摘要翻译： 一种垂直功率MOSFET，其可以提高抗电压耐受电压和抵抗来自电感负载L的浪涌电压的浪涌耐受电压。垂直功率MOSFET具有多个单元电池。 单位电池由在矩形U形槽的侧壁处使用p型基底层作为沟道部分的MOSFET形成。 每个单电池的p型基极层彼此连接。因此，能够抑制矩形p型基极层的角部（位于角部的部分）的杂质浓度降低。 因此，可以减少与p型基底层的端部到耗尽层的端部的距离的差异。 因此，当从电感负载L输入浪涌电压时，可以提高浪涌耐受电压。

公开(公告)号：US20120139079A1

公开(公告)日：2012-06-07

申请号：US13296832

申请日：2011-11-15

申请人： Norihito TOKURA ,  Satoshi Shiraki ,  Shigeki Takahashi ,  Shinya Sakurai ,  Takashi Suzuki

发明人： Norihito TOKURA ,  Satoshi Shiraki ,  Shigeki Takahashi ,  Shinya Sakurai ,  Takashi Suzuki

IPC分类号： H01L29/47

CPC分类号： H01L21/76283 ,  H01L27/0814 ,  H01L27/1203 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/08 ,  H01L29/405 ,  H01L29/8611

摘要： A diode has a semiconductor layer and cathode and anode electrodes on a surface of the semiconductor layer. The semiconductor layer has cathode and anode regions respectively contacting the cathode and anode electrodes. The anode region has a first diffusion region having high surface concentration, a second diffusion region having intermediate surface concentration, and a third diffusion region having low surface concentration. The first diffusion region is covered with the second and third diffusion regions. The second diffusion region has a first side surface facing the cathode region, a second side surface opposite to the cathode region, and a bottom surface extending between the first and second side surfaces. The third diffusion region covers at least one of the first corner part connecting the first side surface with the bottom surface and the second corner part connecting the second side surface with the bottom surface.

摘要翻译： 二极管在半导体层的表面上具有半导体层和阴极和阳极电极。 半导体层具有分别与阴极和阳极电极接触的阴极和阳极区域。 阳极区域具有表面浓度高的第一扩散区域，具有中间表面浓度的第二扩散区域和具有低表面浓度的第三扩散区域。 第一扩散区被第二和第三扩散区覆盖。 第二扩散区域具有面对阴极区域的第一侧表面，与阴极区域相对的第二侧表面和在第一和第二侧表面之间延伸的底表面。 第三扩散区域覆盖连接第一侧表面与底表面的第一角部和将第二侧表面与底表面连接的第二角部中的至少一个。

公开(公告)号：US20110073904A1

公开(公告)日：2011-03-31

申请号：US12923469

申请日：2010-09-23

申请人： Youichi Ashida ,  Norihito Tokura ,  Shigeki Takahashi ,  Yoshiaki Nakayama ,  Satoshi Shiraki ,  Kouji Senda

发明人： Youichi Ashida ,  Norihito Tokura ,  Shigeki Takahashi ,  Yoshiaki Nakayama ,  Satoshi Shiraki ,  Kouji Senda

IPC分类号： H01L29/739 ,  H01L29/06 ,  H01L29/78 ,  H01L21/762

CPC分类号： H01L27/1203 ,  H01L21/76264 ,  H01L21/84 ,  H01L29/0634 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/1608 ,  H01L29/404 ,  H01L29/405 ,  H01L29/407 ,  H01L29/408 ,  H01L29/66128 ,  H01L29/7394 ,  H01L29/7824 ,  H01L29/8611

摘要： A semiconductor device includes: a SOI substrate; a semiconductor element having first and second impurity layers disposed in an active layer of the SOI substrate, the second impurity layer surrounding the first impurity layer; and multiple first and second conductive type regions disposed in a part of the active layer adjacent to an embedded insulation film of the SOI substrate. The first and second conductive type regions are alternately arranged. The first and second conductive type regions have a layout, which corresponds to the semiconductor element.

摘要翻译： 半导体器件包括：SOI衬底; 半导体元件，其具有设置在所述SOI衬底的有源层中的第一和第二杂质层，所述第二杂质层围绕所述第一杂质层; 以及设置在与SOI衬底的嵌入式绝缘膜相邻的有源层的一部分中的多个第一和第二导电类型区域。 交替地布置第一和第二导电类型区域。 第一和第二导电类型区域具有对应于半导体元件的布局。